DCU operating modes

[falstaff]

Hi,

Internal tests have shown different operating modes being used than documented. The Reference Manual Rev. 7 states for the field DCU_MODE in DCUx_DCU_MODE register:

	DCU operating mode
00	DCU off (pixel clock active if enabled by I/O).
01	Normal mode. Panel content controlled by layer configuration.
10	Test mode. DCU disables all DMA fetches and all the pixels of an enabled layer take the value in the CLUT RAM selected by the respective LUOFFS field of control descriptor 4.
11	Color Bar Generation. Panel content controlled by color bar registers.

Hence, clearing the DCU_MODE register using something like DCU_MODE & ~0x3 should turn off the DCU controller, however tests on MVF61 and MVF50 parts have shown that when clearing the DCU_MODE field, the DCU controller seems to enter the test mode. However, when using 0x2, which should be the Test mode, the display stays off (hence this seems to be the DCU off mode).

Is this a documentation error? Can somebody confirm?

Best regards,

Stefan Agner

[alejandrolozan1 · Accepted solution]

Hi Stefan,

I have tested in the MVF61GS which is found in the TWR system and the DCU MODE operation works as expected.

MASK set is 1N02G. Are your facing the same issue in the TWR system?

/Alejandro

[falstaff]

Hi Alejandro,

Sorry, you are right, DCU works as expected.

The DCU off mode left the pixel clock on as documented, which in turn enabled a test mode in my display! Without reading the exact description of the DCU test mode, I assumed that the test mode I saw is generated by DCU... However, when using the DCU test mode, the screen stayed black since I did not had any look up tables (LUOFFS) configured.

This lead me to the conclusion that the DCU operating modes were mixed up...

Sorry about the noise and thanks for verifying this.

--

Stefan