Configurable interval of DMA_ACT of Vybrid.

[takashitakahash]

HI community.

Our customer has question below.

About  the configurable interval of DMA_ACT.

Is it correct my understanding of the below comments.

Vybrid RM description .

57.5.10 DMA and De-interlace

After doing some necessary register configuration, such as coefficients, INVSZ and

DMA_ADDR, user can activate DMA by setting the DMA_ACT of the status and

configuration register. But note that DMA_ACT can be configured only during vertical

blanking since the VIU3 block will not transfer a fragment of video field to memory. If it

is configured during field active time, DMA transfer cannot be started and an error

interrupt will be asserted.

<Question>

Specifically, it can be set " 1 " to DMA_ACT , It is only within the interrupt handler by DMA_END_IRQ( Transfer the end of the video period) , and in the interrupt handler by VSYNC_IRQ .

.

[takashitakahash]

Dear Karina- san,

Thank you for reply.

When is a way that had you suggested,

- Access occurs in the DDR memory in spite of not display.
- Applications and DCU can use at 2frames.(1 → 2,2 → 3.3 begins overwritten with the new data by past the discard.)

The above is the understanding. However, please suggest the best method from the following reasons.

- Even without access to the buffer of discard, I want to as long as possible time that can be used in other than the VIU
- Simply may be increased buffer, but the use of RAM has been tight, want to reduce as much as possible.

<Question>

Without the buffer access for discard, Is there a way to  throw away.

(For example. If  throw away, as it is allowed to stand without DMA_ACT,did on the process in the next Vysnc, I can use a method such as the DMA_ACT.

[karina_valencia]

takashitakahashi​ did you get previous update?

[karina_valencia]

jiri-b36968​  FYI

[jiri-b36968]

Hello Takashi-san,

not sure if I understand:

You want to display every second frame. De-interlace?

so you should ignore every second framer.

Not sure how your driver does it, but you can do it for example like this:

Ext image  transfer address

1               buffer [0]     display

2               buffer [1]     discard

3               buffer [1]     display

4               buffer [0]     discard

5               buffer [0]     display

/Jiri

[takashitakahash]

Dear Jiri-san.

Thank you for your replay.

I have about external input image format question.

For external input, transfer control of 2nd image.

[b] 1(1st) image transfer completed and the buffer address setting after the next 2nd image transfer restart.

External has been received to 60fps (every 16.6ms) from, but we would like to thinning as follows without changing the input from the outside.

-------------------------------------------------- ------------------------------------------------------------------------
External image                            ①              ②               ③                ④                  ⑤
Transfer start address         buffer [0]       discard       buffer [1]      discard           buffer [2]
-------------------------------------------------- --------------------------------------------------------------------------

As the implementation method, we thought should be the control of the [b] at the time of an odd number of times of Vsync interrupt.

But, remaining data that was not received in an even number of times is in the FIFO, and is concerned that than would wreckage of the data is entered into the next buffer.

Could you suggest the implementation method.

[karina_valencia]

jiri-b36968​ can you share your comments?

[timesyssupport]

Hi Takashi,

From the DMA and De-interlace (57.5.10) and Initialization Information(57.6) description, It's looks like DMA_ACT bit(27th bit field) can be set by using VIU3_SCR Configuration Register to start FIFO and DMA transfer. So this operation actually starts the VIU3 to operate.

The DMA_ACT bit is not within the DMA_END_IRQ interrupt handler instead "DMA_ACT" is part of VIU3 Status And Configuration Register bit(VIU3_SCR).

You could refer the 57.6.1 Initialization Information from the following vybrid reference manual link for more information.

http://cache.nxp.com/files/microcontrollers/doc/ref_manual/VYBRIDRSERIESRM.pdf?fsrch=1&sr=3&pageNum=...

Thanks,

Timesys Support

[takashitakahash]

Hi community.

As RM explains that DMA_ACT should be set during VSYNC period.

My understanding is that VSYNC_IRQ is set at start point of VSYNC and VSTART_IRQ is set at end of VSYNC.
I guess DMA_END_IRQ is set within VSYNC.

So My understanding is that DMA_ACT can set between DMA_END_IRQ and VSTART. Could you confirm it ?

This is HW question, so please include HW team, too.

[timesyssupport]

Hi karinavalencia​,

Can the NXP Vybrid Hardware team please comment on this?

Thanks,

Timesys Support

[jiri-b36968]

Hello Takashi-san,

Transfer of layer configuration registers have to be done at proper moment.

Flags and interrupt sources are available and have to be used.

It is not allowed to attempt registers during transfer of configuration into DCU logic.

More here: please look at DCU_layer_transfer_issue_3.pdf just uploaded.

/Jiri

[karina_valencia]

timesyssupport​ can you help here?