Using 1000base-kx on a T1042

[hanshamb]

I am completely new to NXP, QorIQ, Yocto, identifying and adding out-of-tree modules (drivers), RCW, and so much more. I am struggling with enabling 1000base-kx on a T1042D4RDB system. I've mentally pieced together many web pages, since there don't seem to be any straight-forward instructions anywhere, but my knowledge still has gaping holes.

I started here: Ls1046a 1000Base-KX/10gBase-KR Linux support.

The solution is "There a few more bits to set along with clearing the AMP_RED field", which is not useful,  but it does point to these two pages:

lf-6.6.y fman 

Eval Board for 1000Base-KX LS1046A ? 

So far, I think I need to:

1. Download the nxp-qoriq/linux source from GitHub
   • Done
2. Compile the source for the T1042 processor
   • GNU Make >= 3.82 is required. Your Make version is 8.81. Stop
3. Create a driver module
   • I plan to utilize Incorporating Out-of-Tree Modules in YOCTO
   • I have many doubts and questions about a 1000base-kx driver
4. Edit the RCW
   • Discussed Below
5. Configure / create an SGMII device?
   • This might be easier once #4 has been completed.
   • I may just need to create and write the RCW binary
6. Create a 1000base-kx connection using the SGMII?

Any guidance would be appreciated.

For #4, I need to convert from RR_P_86 (default) to RR_S_86.

I think this involves:

• Starting here: GitHub: nxp-qoriq/rcw 
• Copying t1042d4rdb/RR_P_86/rcw_1400MHz.rcw to t1042d4rdb/RR_S_86/rcw_1400MHz.rcw
• Editing rcw_1400MHz.rcw to change ... something?
• Converting to binary using rcw.py?

Maybe I can make more sense of the statements in Eval Board for 1000Base-KX LS1046A ?, but I currently don't understand what to do for lines like:

• LNmGCR1 [REIDL_TH]
• LNmGCR1 [REIDL_EX_SEL]
• LNmGCR1 [REIDL_ET_MSB]
• LNmTECR0 [AMP_RED]

or how to reconcile:

• SGMII_EN = 0
• USE_SGMII_AN = 0
• SGMII_SPEED = 10

with anything in t1042d4rdb/RR_P_86/rcw_1400MHz.rcw, t1040si/t1040.rcwi, or t1040si/a007662.rcw:

And then there's this: Instead, a SerDes reference clock is required on SD1_REF_CLK[1:2]_P and

SD1_REF_CLK[1:2]_N pins.

[yipingwang]

It does not need to modify RCW as 1000Base-KX is supported on all SGMII lanes, and the default t1042d4rdb/RR_P_86/ had selected SGMII.

Customer can refer to Please refer to chapter 31.6.1.3 1000Base-KX to initialize 1000base-kx.
The following are registers which need to be set.
"
• SRDSx_LNmGCR1[REIDL_TH]
• SRDSx_LNmGCR1[REIDL_EX_SEL]
• SRDSx_LNmGCR1[REIDL_ET_MSB]
• SRDSx_LNmTECR0[AMP_RED]
"

Meantime, it can also refer to t208xqds implementation.
1000BASE-KX(1G-KX):
- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
initialization.
Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.