T4240RDB RCW Configuration

[vinothkumars]

Hi All,

How we will calculate the SYSCLK and DDRCLK using hard-coded Reset Configuration Word (RCW) to T4240RDB.

Please give some detailed explanation.

Hard-Coded RCW Value,

Data.Set DBG:0x01000000 0x1406000A
Data.Set DBG:0x01000001 0x0A080808
Data.Set DBG:0x01000002 0x00000000
Data.Set DBG:0x01000003 0x00000000
Data.Set DBG:0x01000004 0x6C6E2848
Data.Set DBG:0x01000005 0x30548c00
Data.Set DBG:0x01000006 0xFC02F000
Data.Set DBG:0x01000007 0x1D000000
Data.Set DBG:0x01000008 0x00000000
Data.Set DBG:0x01000009 0xEE0000EE
Data.Set DBG:0x0100000A 0x00000000
Data.Set DBG:0x0100000B 0x000307FC
Data.Set DBG:0x0100000C 0x00000000
Data.Set DBG:0x0100000D 0x00000000
Data.Set DBG:0x0100000E 0x00000000
Data.Set DBG:0x0100000F 0x00000008

Thank you for everyone help........!

Regards, Vinoths

[alexander_yakov · Accepted solution]

For clock module structure please look Figures 4-2, 4-3 and 4-4 in T4240 Reference Manual.

SYSCLK and DDRCLK are inputs to clock module, so I assume you are asking about System PLL and DDR PLL multipliers. These multipliers are encoded in first two bytes of RCW. Please look T4240 Reference Manual, Table 4-13.

In your case first two bytes are 0x1406 or 0001 0100 0000 0110 binary, this results to:

SYS_PLL_CFG = "00"

SYS_PLL_RAT = "01010" - ratio 10:1

MEM_PLL_CFG = "00"

MEM_PLL_RAT = "000110" - ratio 12:1

Have a great day,
Alexander
TIC

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