I'm trying to gain a better understanding of the entire boot sequence of the processor. I'm debugging the T4240QDS and stepping through assembly to try and reach a point in the code that is familiar (like, jumping to the PBL or jumping to the entry address of uBoot) but I have not reached that point yet. I'm beginning to wonder about the exact steps taken by the processor from power on until it Boots. I've read chapters 4 (the part about the RCW) and chapter 5 and have gained a better 3000-meter understanding of what goes on, but I'm still at a loss as the jumps that the processor takes in order to reach those points.
Here's my understanding of the process (please correct me if I'm wrong).
- The processor is powered on and always starts at 0xffff_fffc (core 0 thread 0).
- POR reset signals sample the POR signals from the board and write them to registers on the CCSR space.
--This address has a branch instruction to where the processor (still core 0 thread 0) needs to run next (I'm still not exactly sure where this code is coming from).
-The PBL containing the RCW gets loaded (assuming that option is set, i.e. NOR flash on SW1) from the current base address of flash (that base address varies depending on your SW6 settings).
- The processor (core0 thread 0) runs some more initialization code (some insight on this code would be helpful too!).
-At some point, the processor jumps to 0xeff8_0000 and copies uBoot into DDR to run (all cores can now be handed tasks).
Here are my questions:
1.) I'm confused as to how the processor knows that 0xeff8_0000 is where uBoot resides. Further confusion stems from the fact, when we wanted to boot from a vxWorks bootrom in bank 5, we had to place it at a different offset (0xeaf0_0000) for it to work...I thought we would just put it at 0xeaf8_0000.
We used the exact same PBL from bank 0 and put it in what becomes the base of flash when we switch SW6 to bank 5 (0xed00_0000). This leads us to believe that the PBL has no role in what location in flash the processor pulls the bootrom from. How/where does the processor determine the location of the bootloader? Is this an address that can be set/changed?
2.) Stemming from thread LS1021a full boot sequence , it sounds like there is a separate component of the SoC that actually reads in the PBL (PBL block) and core0-thread0 never even sees the PBL. Is the same true for the T4240? Does it also have a block that reads it? I saw in Chapter 5 of the T4240RM it talks about the PBL Common Control Logic.
General reference to the reset sequence is QorIQ T4240 Reference Manual, 4.6.1 Power-on reset sequence
1) You wrote:
> I'm confused as to how the processor knows that 0xeff8_0000 is where uBoot resides.
Please note that 0xeff8_0000 is U-Boot starting address in the U-Boot memory map.
During initial boot the first burst fetch is always performed from the address 0x0_FFFF_FFC0.
In case of NOR Flash and reset settings of the eLBC CS0 this corresponds to the last 64 bytes in the NOR Flash device connected to the CS0.
> This leads us to believe that the PBL has no role in what location in flash the processor pulls the bootrom from.
> How/where does the processor determine the location of the bootloader?
QorIQ T4240 Reference Manual, 5.5.1 Starting addresses
2) You wrote:
> there is a separate component of the SoC that actually reads in the PBL (PBL block)
> and core0-thread0 never even sees the PBL. Is the same true for the T4240?
Correct, see step 9 in the 4.6.1 Power-on reset sequence.