I'm trying to understand the full boot sequence of the LS1021a, and I'm a bit confused.
From what I gathered so far from SDK v1.9, the high-level view is:
- PBL code reads the fuses / RCW / PBI commands
- at some point, it copies u-boot from the boot medium to OCRAM and runs it (SD in my case)
- at this point, u-boot can configure DDR, copy Linux into it and boot Linux
What I'm unsure about is:
- Is the PBL executed by Cortex-a7 core 0, or is it an external chip ?
- Is the PBL code located in the ROM section (first Mb of the memory map) ?
- If that's not the case, can we access the PBL code to understand it ?
- In the RCW generated by the SDK (sdcard_ifc), there are lots of PBI instructions which copy code to OCRAM (like TZASC, IFC, SATA config ...) but I don't understand when the control branch to this code.