We are running SYSCLK at 100MHz. We are using PLL1 to drive the FMAN. We use Processor Expert to create the RCW. In the past I have been able to set CGA_PLL1_RAT to 7:1. But now it appears I cannot set it lower than 8:1. Did PE change to limit the value? The reference manual states 5:1 is allowed, but states look elsewhere (datasheet is assumed) to determine limitations.
In the datasheet, Table 121 discusses PLL frequencies. I may have missed the limitation there in the past as I assume it was for the Core frequency, does that require the CGA_PLL1 and CGA_PLL2 to meet a minimum of 1000MHz?
