T1040 VDD (VCORE), VDDC (VCORE_SLP)

[maticmohorcic]

Hi!

I'm designing power supply for T1040 and I have got question regarding it's sequence – step 2 (VDDC, VDD, USB_SVDD, S1VDD).  We will not use Deep Sleep functionallity.  In DS there is written that  When Deep Sleep is not used, it is recommended to source VDD and VDDC from same power supply. But in AN4825 there written that VDDC should ramp before VDD.

I'm studying T1040 reference design but there is something unclear for me. On the page 29 there is VCORE and VCORE_SLP and both outputs are connected together. But there are 2 mosfets on the page 31 which separates VCORE_SLP and VCORE => It is quite confusing

Do we need to use FET to separate VDDC and VDD ( different power up timing) or not?

Could you please answer my question asap because we are finishing our project.

Best Regards Matic 

[r8070z]

Have a great day,

If you do not use Deep Sleep functionality, then you do not need to use FET to separate VDDC and VDD for sure.

From my point of view, the design check list document does not contradict to the datasheet. It also says ‘VDDC should ramp up along with or before VDD power supply’ and refers to the datasheet - ‘Care should be taken to ensure that relative timing between VDDC and VDD conforms as per the "VDDC and VDD ramp up diagram" in chip datasheet’.

On attached picture (T1040RDB schematics p. 29) I see that VCORE is not connected to VCORE_SLP directly. It looks like VCORE is just connected to one of the 4 capacitors.

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[maticmohorcic]

Hi Serguei!

At first I need to thank you for quick reply! It is so confusing because I received different answer (separated VDD and VDDC) from the other guy from NXP support. Could you please recheck VDD and VDDC connections?

Best Regards Matic

[r8070z · Accepted solution]

I am quite sure that the T1040 datasheet permits to connect VDD pins and VDDC pins to the same power supply. Notice there are several statements for that - the (a.) says that directly; or the same can be derived from statement (b.) and Figure 9. Next now we have the rev.2 document so there is very low probability for misprint or erratum which was not taken into account (I also have checked the T1040 errata).

It is obvious that we have to provide power switch from VDDc to VDD or use separate power supply for VDD if we want have VDD=0 while VDDC is ON (both variants are shown in the design guide). If we do not need to switch off VDD than we can connect VDD pins and VDDC pins to the SAME power rail and it is recommended. The datasheet says “a. When Deep Sleep is not used, it is recommended to source VDD and VDDC from same power supply.”

If we have separated VDDC then there is requirement for the power sequence VDDC and VDD which is actually limited by Figure 9 in the datsheet. Of course the RDB board schematics does not say that VDD and VDDC cannot be connected in any other design. They are not connected on the RDB schematics because the RDB board implements possibility for the Deep Sleep.

[r8070z]

So you should ask that guy why he requests for the separated VDD and VDDC (or more exactly for delay in beetween VDD and VDDC ramps).