T1024 UART getting Overrun errors

[ramkrishnan]

On our setup we have a backplane in which multiple types of boards are connected. One of them is a new board which is T1024 based and the backplane communication is serial. 

The T1024 is configured to have 4 UART's i.e there are not CTS/RTS for the DUARTs. They are configured to be UART3_SOUT/SIN and UART4_SOUT/SIN in the rcw.

The backplane speed is set to 2062500 bits per second. There are older cards which are 8250 and are able to handle that speed and is able to transfer big files across the serial line but it fails with the T1024. 

I have used stty to set the parameters for the port to disable all modem and any echos i.e keep it raw.

One thing I do see is that on the T1024 even though the UART register FE11C602 is set to E1 , the interrupts are occurring on a per byte basis. This I see it from the /proc/interrupts going up by the number of bytes or somewhere close to it. While in the older cards it goes up by buffer lengths i.e around 200 bytes per interrupt. 

Could this be the problem as to why it is getting overrun. How would I change it to use the FIFO (even though I can see it in the register configuration). 

The divisor is 6 based on the 2062500 baud. The percentage of error is around 1% based on the paltformclock/2 of 200000000 bps. 

Any help in figuring out this issue would be appreciated. 

Thank you,

Ram Krishnan

[ramkrishnan]

Thank you very much Alexander for the reply. I do see that the 8250 is the cpm_uart device driver. I take it that the DMS bit in the UFCR UART register is not usable.

Thanks,

Ram Krishnan 

[alexander_yakov · Accepted solution]

MPC8250 has different type UART, this UART is a part of CPM communication co-processor. This UART is fully handled   by CPM co-processor, it can receive data and transfer it to data buffer in memory by DMA without intervention of main core. When the data is received and moved to buffer memory, CPM can generate interrupt to main core indicating that data buffer reception is finished, and the main core may start processing received data.

The key point here is DMA and interrupt generated only once when full buffer is received.

In contrast with MPC8250' UART, the DUART block works on per-byte basis. That is, it is not managed by any co-processor, each byte received by this DUART must be read by main core and moved to memory by core read/write operations, without using any DMA. There is no DMA support in DUART block, it has only small FIFO for several bytes, this may be helpful to decrease number of interrupts to main core from one per byte to one per FIFO watermark, but this does not help significantly - you still need to read each individual byte from FIFO and transfer it to memory by core read/write operations.

DUART is not very fast. Device datasheet stated the maximum DUART baudrate is (platform frequency)/(2*16), which is 12,5 mbps for 400 Mhz plaftorm, but there is a note that actual baudrate "is limited by the latency of interrupt processing".

That is, you can reach this speed only if you spend all your main core processing time to interrupts.

Obviously, if you have 4 UARTs running simultaneously, you will experience overruns/underruns at high speed, because the core have to process all interrupts from all UARTs simultaneously.

In our recent devices we have "Quicc Engine" (QE), this communication co-processor is a derivative from old CPM, and QE-based UART works in the same way, as old CPM-based UART. So, if you wish to implement similar functionality, I recommend looking QE-based UART.

Have a great day,
Alexander

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