T1022 Clock Sequence

[jack_mcculloch]

Hi,

We are designing a custom board with a T1022 processor and would like to know if the there are any power-on sequencing requirements for the clocks?

Do all power rails need to be valid before clocks are enabled?

Is there minimum time the clocks need to be valid before PORESET_B is lifted?

[Bulat · Accepted solution]

SYSCLK can be applied alone with OVDD/O1VDD supplies.
We do not specify "minimum time the clocks need to be valid before PORESET_B".
Minimum PORESET assertion time is 1ms, use it as a 'clock valid' setup as well.

Regards,

Bulat