T1022 Boot issue

Priyanka_Yadav · ‎11-09-2023

Hello,

We are using T1022NSN7W in our design. We give PORESET_B as low for 400ms. CFG_RCW_SRC0 TO CFG_RCW_SRC8 is set to 0x9E (Hardcoded). But when we probe HRESET_B is coming low and ASLEEP is coming high. What could be the issue.

Priyanka_Yadav · ‎11-13-2023

When we try to bring system up using lauterbach tool by running. cmm file then system comes up and we can read registers SVR PVR and others but not coming up with following two cases :

1. When doing hardcoded (9E) system is not coming up.

2. And also when configuring as SPI boot, the clock, CS, MISO MOSI transactions are seen but processor is not able to boot up.

3. When accessing using lauterbach we are able to bring system up, In this case can we say :

a) RCW configuration is ok and

b) reset sequence is ok,

c) System power is ok

d) SYSCLK is ok.

Please advice...

yipingwang · ‎11-14-2023

Comments:
1. Is it a new design? How many boards have been built? How high is the failure rate?
2. Please provide the schematic.
3. Please provide the waveform that you have measured, such as ASLEEP, PORESET_B, SYSCLK on the same screen and can illustrate their timing relationship and signal integrity.

Priyanka_Yadav · ‎11-20-2023

Apology for delayed response. Please find response inline :

1. Is it a new design? How many boards have been built? How high is the failure rate?

RESPONSE : Yes, it's a new design. 10 boards are assembled. We have tested on four boards.

2. Please provide the schematic.

RESPONSE : PFA processor schematic.

3. Please provide the waveform that you have measured, such as ASLEEP, PORESET_B, SYSCLK on the same screen and can illustrate their timing relationship and signal integrity.

RESPONSE : PFA waveforms. Snapshot '1' shows ASLEEP (Blue color) and PORESET_B(Yellow color).Snapshot '2' shows clock(Pink) and PORESET_B (Yellow color).

yipingwang · ‎11-24-2023

NXP is trying to help the customer, so please request the customer to release the material that let other people outside C-dot can make them useful.

Comments

Please capture the waveform that can illustrate the relationship between SoC signals. For example, search "power-on reset sequence" at the RM. Existing waveform cannot reveal the status.
How is failure rate?
Please generate a schematic that is text searchable. It is not possible to check relevant connections without searching with keyword.

Priyanka_Yadav · ‎11-24-2023

Please capture the waveform that can illustrate the relationship between SoC signals. For example, search "power-on reset sequence" at the RM. Existing waveform cannot reveal the status. RESPONSE : Please find attached clk,poreset and hreset in one frame capture. Yellow is HRESET, BLUE is PORESET and PINK is diff_sysclk.
How is failure rate? RESPONSE : Four cards, out of these 3 are completely failing to boot, one card boots 90% times and 10% times it fails.
Please generate a schematic that is text searchable. It is not possible to check relevant connections without searching with keyword. RESPONSE : Please find attached.

yipingwang · ‎11-26-2023

EVT0_B must be pulled up. If it is not pulled up, it may affect normal boot up.

Please rework the board to confirm it.

yipingwang · ‎11-26-2023

I double checked the datasheet, EVT0 has internal weak pull up, but others EVT pins haven't specified.

At the board, EVT0,1,4 are not externally pulled up. So please pull them up through 2-10k ohm resistors, individually, including EVT0_B.

Some more comments:

Please check for any difference between good and failed conditions. Zoom in and capture, if you found any difference.
What is the power up sequencing? Is GVDD ramp last and PORESET deassert after GVDD becomes nominal?
How is TRST_B asserted? Is it sync with PORESET_B? Check the CPLD equation or confirm with waveform capture.

Priyanka_Yadav · ‎11-30-2023

1. At the board, EVT0,1,4 are not externally pulled up. So please pull them up through 2-10k ohm resistors, individually, including EVT0_B.

RESPONSE : There is no pinout on EVT0,1,4 pins in our board. EVT2 and EVT3 are pulled up on board. We have used T1022 in our other designs also where EVT0,1,4 are left floating and designs are working.

2. Please check for any difference between good and failed conditions. Zoom in and capture, if you found any difference.

RESPONSE : We are working on this.

3. What is the power up sequencing? Is GVDD ramp last and PORESET deassert after GVDD becomes nominal?

RESPONSE : After G1VDD rampup , there is time of 500ms approx and PORESET deassert.

4. How is TRST_B asserted? Is it sync with PORESET_B? Check the CPLD equation or confirm with waveform capture.

RESPONSE : Earlier CPLD equation was : PROC_TRST_N<=COP_TRST_N;

Now, we have changed this to : PROC_TRST_N <= porest_extended and COP_TRST_N;

Also, PROC_PORST_N <= porest_extended and COP_HRESET_N;

Query : We have seen that when we access via JTAG(run rcw.cmm file and then do system up and in target reset), COP_HRESET_N is driven low twice with pulse width of 50ms and gap of around 1.5s between these two pulses. Do we need to replicate this scenario for PROC_PORST_N also. As of now we are giving only single pulse of 400ms.

yipingwang · ‎12-01-2023

Please illustrate the TRST modification/query with waveform. Hand-drafting is OK.

Misunderstanding will happen with text description.

Priyanka_Yadav · ‎12-04-2023

1. Please find attached waveform for Query :

CASE1 : RCW configuration via JTAG : "Hardreset_poreset_JTAGexecution.png". Yellow is PROC_HRESET_N. and Blue is COP_HRESET_N. We run rcw.cmm file in trace32 and capture COP_HRESET_N signal transition.

CASE2 : RCW via SPI boot : "Hardreset_poreset_spiboot.png". We change PROC_PORESET_N to behave similar to COP_HRESET_N to simulate same behaviour. In this case, PROC_HRESET_N comes high first time but never comes high during second time.

2. "poreset_proc_trst_nduring powerup.png" PFA snapshot of PROC_TRST_N on modificaiton. It follows PROC_PORESET_N on modification. PROC_TRST_N is pulled up on JTAG connector.

PROC_TRST_N <= porest_extended and COP_TRST_N;

Earlier it was : PROC_TRST_N <= COP_TRST_N;

Anyways, we didn't see any transition on COP_TRST_N during access via JTAG also, so this mayn't affect functionality during processor boot from SPI.

3. In one card which is booting 90% times, that card was getting stuck at DDR, so we were trying to connect Code Warrior Tool with JTAG but issue is Tool is not scanning the processor. "Board scan" command is running successful(didn't take snapshot for board scan cmd) but scan chain cmd fails to scan and gives timeout error. PFA snapshot for same. Code Warrior cmds.jpg and Code Warrior.jpg.

yipingwang · ‎12-04-2023

Regarding to the capture "Hardreset_porest_spiboot.png", it does not look normal.

Please capture the waveform that can illustrate the relationship between SoC signals. For example, search "power-on reset sequence" at the RM. Existing waveforms cannot reveal the status. Suggest to include ASLEEP.

Priyanka_Yadav · ‎12-05-2023

PFA waveforms.

yipingwang · ‎12-06-2023

Could you label the signal? Anyway, they cannot match to whatever SoC required. PORESET_B should be monotonic low to high at the power up. i.e. Keep low before all voltage rails ramp, until GVDD becomes nominal. No toggling, just single low to high at POR. Suggest to compare the previous produced board. What circuit/component has been modified? Please clean up the reset signal if previous board also has got similar problem.

yipingwang · ‎12-05-2023

Will update later.

yipingwang · ‎12-04-2023

If getting DDR working is the first priority, I suggest focusing on the DDR. JTAG signal integrity is not good.

Please set the verbosity to maximum and dump the u-boot log. Please dump the DDR register in full range.

Priyanka_Yadav · ‎12-06-2023

we have added:
#define DEBUG
in following files:
1. u-boot/board/freescale/t104xrdb/ddr.c
2. u-boot//drivers/ddr/fsl/ctrl_regs.c
3. u-boot/drivers/ddr/fsl/main.c
4. u-boot/drivers/ddr/fsl/options.c
5. u-boot/drivers/ddr/fsl/fsl_ddr_gen4.c
6. u-boot/drivers/ddr/fsl/ddr4_dimm_params.c
7. u-boot/drivers/ddr/fsl/lc_common_dimm_params.c
8. u-boot/drivers/ddr/fs/interactive.c

UBOOT LOG 1 :

Initializing....using SPD

starting at step 1 (STEP_GET_SPD)

DDR: DDR III rank density = 0x 200000000

Computing lowest common DIMM parameters for memctl=0

lowest_common_spd_caslat is 0xb

all DIMMs ECC capable

tCKmin_ps = 625

trcd_ps = 13750

trp_ps = 13750

tras_ps = 32000

trfc1_ps = 350000

trfc2_ps = 260000

trfc4_ps = 160000

trrds_ps = 2500

trrdl_ps = 4900

tccdl_ps = 5000

twr_ps = 15000

trc_ps = 45750

Reloading memory controller configuration options for memctl=0

WARNING: Calling __hwconfig without a buffer and before environment is ready

mclk_ps = 1250 ps

WARNING: Calling __hwconfig without a buffer and before environment is ready

Found timing match: n_ranks 1, data rate 2400, rank_gb 4

clk_adjust 4, wrlvl_start 6, wrlvl_ctrl_2 0x708090b, wrlvl_ctrl_3 0xc0d0d0a

0 of 1 controllers are interleaving.

Checking interleaving options completed

dbw_cap_adj[0]=0

ctrl 0 dimm 0 base 0x0

ctrl 0 total 0x200000000

Total mem by __step_assign_addresses is 0x200000000

Total mem 8589934592 assigned

FSL Memory ctrl register computation

FSLDDR: cs[0]_bnds = 0x000001ff

FSLDDR: cs[0]_config = 0x80040422

FSLDDR: cs[0]_config_2 = 0x00000000

FSLDDR: cs[1]_bnds = 0x00000000

FSLDDR: cs[1]_config = 0x00000000

FSLDDR: cs[1]_config_2 = 0x00000000

FSLDDR: timing_cfg_0 = 0x91550018

FSLDDR: timing_cfg_3 = 0x01111000

FSLDDR: timing_cfg_1 = 0xbab40c42

FSLDDR: timing_cfg_2 = 0x0048c111

FSLDDR: ddr_cdr1 = 0x80040000

FSLDDR: ddr_cdr2 = 0x0000a180

FSLDDR: ddr_sdram_cfg = 0xe5040008

DDR: ddr_data_init = 0xdeadbeef

FSLDDR: ddr_sdram_cfg_2 = 0x00401110

FSLDDR: ddr_sdram_mode = 0x03010210

FSLDDR: ddr_sdram_mode_3 = 0x00010210

FSLDDR: ddr_sdram_mode_5 = 0x00000000

FSLDDR: ddr_sdram_mode_2 = 0x00000000

FSLDDR: ddr_sdram_mode_4 = 0x00000000

FSLDDR: ddr_sdram_mode_6 = 0x00000000

FSLDDR: ddr_sdram_mode_8 = 0x00000000

FSLDDR: ddr_sdram_mode_9) = 0x00000500

FSLDDR: ddr_sdram_mode_11 = 0x00000400

FSLDDR: ddr_sdram_mode_13 = 0x00000000

FSLDDR: ddr_sdram_mode_15 = 0x00000000

FSLDDR: ddr_sdram_mode_10) = 0x00000000

FSLDDR: ddr_sdram_mode_12 = 0x00000000

FSLDDR: ddr_sdram_mode_14 = 0x00000000

FSLDDR: ddr_sdram_mode_16 = 0x00000000

FSLDDR: ddr_sdram_interval = 0x18600618

FSLDDR: clk_cntl = 0x02000000

FSLDDR: timing_cfg_4 = 0x00000002

FSLDDR: timing_cfg_5 = 0x03401400

FSLDDR: ddr_sdram_cfg_3 = 0x00000000

FSLDDR: timing_cfg_6 = 0x00000000

FSLDDR: timing_cfg_7 = 0x23300000

FSLDDR: timing_cfg_8 = 0x01004600

FSLDDR: timing_cfg_9 = 0x00000000

FSLDDR: dq_map_0 = 0x5b65b658

FSLDDR: dq_map_1 = 0xd96d96d8

FSLDDR: dq_map_2 = 0x5b65b658

FSLDDR: dq_map_3 = 0xd96d8001

FSLDDR: zq_cntl = 0x8a090705

FSLDDR: wrlvl_cntl = 0x8675f606

FSLDDR: wrlvl_cntl_2 = 0x0708090b

FSLDDR: wrlvl_cntl_3 = 0x0c0d0d0a

Programming controller 0

total 8 GB

Need to wait up to 268 * 10ms

total_memory by __fsl_ddr_sdram = 8589934592

6 GiB left unmapped

Loading second stage boot loader .................................................................................................

UBOOT LOG 2 where we get "D_INIT timeout."

Initializing....using SPD

starting at step 1 (STEP_GET_SPD)

DDR: DDR III rank density = 0x 200000000

Computing lowest common DIMM parameters for memctl=0

lowest_common_spd_caslat is 0xb

all DIMMs ECC capable

tCKmin_ps = 625

trcd_ps = 13750

trp_ps = 13750

tras_ps = 32000

trfc1_ps = 350000

trfc2_ps = 260000

trfc4_ps = 160000

trrds_ps = 2500

trrdl_ps = 4900

tccdl_ps = 5000

twr_ps = 15000

trc_ps = 45750

Reloading memory controller configuration options for memctl=0

WARNING: Calling __hwconfig without a buffer and before environment is ready

mclk_ps = 1250 ps

WARNING: Calling __hwconfig without a buffer and before environment is ready

Found timing match: n_ranks 1, data rate 2400, rank_gb 4

clk_adjust 4, wrlvl_start 6, wrlvl_ctrl_2 0x708090b, wrlvl_ctrl_3 0xc0d0d0a

0 of 1 controllers are interleaving.

Checking interleaving options completed

dbw_cap_adj[0]=0

ctrl 0 dimm 0 base 0x0

ctrl 0 total 0x200000000

Total mem by __step_assign_addresses is 0x200000000

Total mem 8589934592 assigned

FSL Memory ctrl register computation

FSLDDR: cs[0]_bnds = 0x000001ff

FSLDDR: cs[0]_config = 0x80040422

FSLDDR: cs[0]_config_2 = 0x00000000

FSLDDR: cs[1]_bnds = 0x00000000

FSLDDR: cs[1]_config = 0x00000000

FSLDDR: cs[1]_config_2 = 0x00000000

FSLDDR: timing_cfg_0 = 0x91550018

FSLDDR: timing_cfg_3 = 0x01111000

FSLDDR: timing_cfg_1 = 0xbab40c42

FSLDDR: timing_cfg_2 = 0x0048c111

FSLDDR: ddr_cdr1 = 0x80040000

FSLDDR: ddr_cdr2 = 0x0000a180

FSLDDR: ddr_sdram_cfg = 0xe5040008

DDR: ddr_data_init = 0xdeadbeef

FSLDDR: ddr_sdram_cfg_2 = 0x00401110

FSLDDR: ddr_sdram_mode = 0x03010210

FSLDDR: ddr_sdram_mode_3 = 0x00010210

FSLDDR: ddr_sdram_mode_5 = 0x00000000

FSLDDR: ddr_sdram_mode_2 = 0x00000000

FSLDDR: ddr_sdram_mode_4 = 0x00000000

FSLDDR: ddr_sdram_mode_6 = 0x00000000

FSLDDR: ddr_sdram_mode_8 = 0x00000000

FSLDDR: ddr_sdram_mode_9) = 0x00000500

FSLDDR: ddr_sdram_mode_11 = 0x00000400

FSLDDR: ddr_sdram_mode_13 = 0x00000000

FSLDDR: ddr_sdram_mode_15 = 0x00000000

FSLDDR: ddr_sdram_mode_10) = 0x00000000

FSLDDR: ddr_sdram_mode_12 = 0x00000000

FSLDDR: ddr_sdram_mode_14 = 0x00000000

FSLDDR: ddr_sdram_mode_16 = 0x00000000

FSLDDR: ddr_sdram_interval = 0x18600618

FSLDDR: clk_cntl = 0x02000000

FSLDDR: timing_cfg_4 = 0x00000002

FSLDDR: timing_cfg_5 = 0x03401400

FSLDDR: ddr_sdram_cfg_3 = 0x00000000

FSLDDR: timing_cfg_6 = 0x00000000

FSLDDR: timing_cfg_7 = 0x23300000

FSLDDR: timing_cfg_8 = 0x01004600

FSLDDR: timing_cfg_9 = 0x00000000

FSLDDR: dq_map_0 = 0x5b65b658

FSLDDR: dq_map_1 = 0xd96d96d8

FSLDDR: dq_map_2 = 0x5b65b658

FSLDDR: dq_map_3 = 0xd96d8001

FSLDDR: zq_cntl = 0x8a090705

FSLDDR: wrlvl_cntl = 0x8675f606

FSLDDR: wrlvl_cntl_2 = 0x0708090b

FSLDDR: wrlvl_cntl_3 = 0x0c0d0d0a

Programming controller 0

total 8 GB

Need to wait up to 268 * 10ms

Waiting for D_INIT timeout. Memory may not work.

total_memory by __fsl_ddr_sdram = 8589934592

6 GiB left unmapped

Loading second stage boot loader

yipingwang · ‎12-06-2023

Please use QCVS DDRv tool to do DDR optimization and validation.

Priyanka_Yadav · ‎12-06-2023

As also said earlier ,

In one card which is booting 90% times, that card was getting stuck at DDR, so we were trying to connect Code Warrior Tool with JTAG but issue is Tool is not scanning the processor. "Board scan" command is running successful(didn't take snapshot for board scan cmd) but scan chain cmd fails to scan and gives timeout error. PFA snapshot for same. Code Warrior cmds.jpg and Code Warrior.jpg.

yipingwang · ‎12-06-2023

Please configure the target board as hard-coded RCW to check whether "ccs::config_chain t1020" can be executed successfully.

If still no, it means there is JTAG interface hardware design issue. Please refer to "Figure 25. JTAG interface connection" in AN4825.

Priyanka_Yadav · ‎12-10-2023

In one of card (card number 69) , we have configured as HARDCODED 9E, but still processor doesn't come up and shows following error in message of lauterbach tool. "HARDCODED_CPUSettings_InTargetReset"

Also, when we verify by running RCW.cmm in tool and then read the DCPC registers, the RCW_SRC is read as 9E. Also, we have observed that this 9E toggle between 9E and 9F sometimes. Although it's actually set to 9E. Two snapshots for this : 1. HARDCODED_run RCWcmm_CPUSettings_InTargetReset and 2. DCPC when Hardcoded_runRCWcmm_CPUSettings_InTargetReset

PFA images snapshots.

If still no, it means there is JTAG interface hardware design issue. Please refer to "Figure 25. JTAG interface connection" in AN4825.

RESPONSE : We are able to program and verify the SPI flash.

We are able to program and verify NAND Flash.

We are succesfully able to run RCW.cmm and bring processor up and do in-Target-Reset when configured 45h(SPI Boot) and it is always consistently successful.