PBI Command For T2080 I2C EEPROM Boot

[vidyasagartata]

Dear All,

We are loading RCW from i2c EEPROM.

Please let us know how to add PBI command in RCW to boot from NOR flash.

We tried disabling the PBI source in RCW and IFC boot_mode set as NOR flash but log shows boot from NAND.

We are getting below u-boot logs:

U-Boot 2016.012.0+ga9b437f (Aug 14 2016 - 12:07:29 +0530)

CPU0:  T2080E, Version: 1.1, (0x85380011)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:533.280 MHz, CPU1:533.280 MHz, CPU2:533.280 MHz, CPU3:533.280 MHz,
       CCB:599.940 MHz,
       DDR:533.320 MHz (1066.640 MT/s data rate) (Asynchronous), IFC:149.985 MHz
       FMAN1: 133.320 MHz
       QMAN:  299.970 MHz
       PME:   599.940 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 12040008 08000000 00000000 00000000
       00000010: 6c290002 70004200 fc027000 81000000
       00000020: 00800000 00000000 00000000 000323fc
       00000030: 00000000 00800009 00000000 00000004
I2C:   ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NAND
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ
SPI:   ready
DRAM:  Initializing....using SPD
DIMM 0: is not a DDR3 SPD.
Error: No valid SPD detected.
*** failed ***
initcall sequence effc7270 failed at call eff4e9b8 (err=1)
### ERROR ### Please RESET the board ###

This is our RCW data.

AA55 AA55  010E 0100  1204 0008  0800 0000
0000 0000  0000 0000  6C29 0002  7000 4200
FC02 7000  8100 0000  0080 0000  0000 0000
0000 0000  0003 23FC  0000 0000  0080 0009
0000 0000  0000 0004  0813 8040  5191 3F4C

Please verify our RCW and suggest us.

We are using discrete DDR.

Thanks,

Vidya

[ufedor]

> Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NAND

This string is printed after acquiring data from the T2080RDB on-board CPLD - refer to:

sdk/u-boot.git - Freescale PowerPC u-boot Tree 

"NAND" can be printed if the CPLD is not implemented.

[vidyasagartata]

Dear Fedor,

Thanks for reply, your suggestion worked and getting below log:

Problem : We are using discrete DDR3 on chip, why  "DRAM:  Initializing....using SPD".

I have  done #undef CONFIG_DDR_SPD and written QCVS DDR3 generated parameter in config file.

Any other configuration is required to configure

U-Boot 2016.01 (May 15 2017 - 09:02:14 +0530)

CPU0:  T2080E, Version: 1.1, (0x85380011)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:533.280 MHz, CPU1:533.280 MHz, CPU2:533.280 MHz, CPU3:533.280 MHz,
       CCB:533.280 MHz,
       DDR:933.310 MHz (1866.620 MT/s data rate) (Asynchronous), IFC:133.320 MHz
       FMAN1: 133.320 MHz
       QMAN:  266.640 MHz
       PME:   533.280 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 10070008 08000000 00000000 00000000
       00000010: 6c290002 70004200 fc027000 81000000
       00000020: 00800000 00000000 00000000 000323fc
       00000030: 00000000 00800009 00000000 00000004
I2C:   ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NOR vBank0
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI:   ready
DRAM:  Initializing....using SPD
16 MiB (DDR not enabled)

Thanks,

Vidya

[ufedor]

It is reasonable to create new question for the "SPD" issue.