Please look e6500 Core Reference Manual, Chapter 10 "Execution Timing"
Table 10-4 shows "instruction latencies". In this table you can see two columns - "latency" and "repeat time". For example, for floating point multiply instruction "fmul" there will be 1 and 7. This means each instruction takes 7 clocks, but you can issue these instructions one-by-one at every clock in pipelined mode and have a result at every cycle.
Direct link to e6500 Core Reference Manual:
http://www.nxp.com/assets/documents/data/en/reference-manuals/E6500RM.pdf
Have a great day,
Alexander
TIC
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