HRESET_B Problem in Power On Reset Sequence

[athershehzad]

SIr,

I am using a custom made T1042 based card. I am having problem in one card because of power on sequence of the card. A CPLD is used to follow the power on sequence. As a start when I pull down the PORESET_B signal, then according to power-on reset sequence that is mentioned in Figure 4-1 of reference manual, HRESET_B should also get pull down but this is not happening. HRESET_B is continuously on HIGH state resulting not following POWER on sequence. Hence ASLEEP LED is always on. What might be the issue and the solution to this problem?

I have other boards also with same design but they are not causing this issue with same CPLD Code. 

Regards,

Ather

[athershehzad]

Thanks UFedor for your help.

I am using hard-coded RCW settings. 

Following are the waveforms of signals with respect to PORESET_B.

Upper signal is PORESET_B and the trigger of the scope is set on the falling edge of this signal. The other wave is HRESET_B in first picture and RESET_REQ_B in the later one.

[ufedor]

How SYSCLK is applied?

What is the IFC_WE0_B voltage?

[athershehzad]

SYSCLK is 100 MHz single ended clock generated by an oscillator. 

IFC_WE0_B was initially at high impedence state. When PORESET_B was asserted , then it come to 1.8V as shown in the following picture.

Regards

Ather

[ufedor]

Please confirm that TRST_B is asserted during POR.

[athershehzad]

Yes TRST_B is also asserted alongwith poreset_b

[ufedor · Accepted solution]

Please refer to the processor's Data Sheet and Design Checklist to ensure that it is connected and powered correctly.

Also it could be useful to refer to the T1042D4RDB design data available at:

https://www.nxp.com/downloads/en/printed-circuit-boards/T1042D4RDB-PA_DF.zip 

[athershehzad]

Thanks @Ufedor for your help.

As per your suggestion, I checked powers of the board and came to know that VCORE was not proper. So after resolving the issue in the power, scenarios of HRESET_B and RESET_REQ_B are changed. 

Now HRESET_B gets low after PORESET_B but does not pull high after PORESET_B gets high.

Following are the updated pictures of the signals.

[ufedor]

What is the RCW source?

Please ensure that valid RCW is provided during POR.

[athershehzad]

Hard-coded RCW setting is being used.

[ufedor]

Please consider that SerDes PLLs are not powered down and 125 MHz reference clocks have to be applied.

[athershehzad]

Thanks ufedor‌ for your help and your precious time. 

My board is now in working state. The problem that I identified is that due to faulty TTL to MAX232 coverter IC , I was always receiving high on RX of Debug UART. Hence it was not following Power on reset sequence. Apparently this should not be an issue so I overlooked it previously. But when I disconnected the RX signal from MAX232 IC, the board is now powering up properly. 

Would you please comment on this issue because my other boards also don't follow power on reset sequence when TTL UART is connected to the board.

[akhil0805]

What is the significance of UART1_SIN & UART1_SOUT in reset sequence? 

[ufedor]

> when TTL UART is connected to the board.

What do you mean?

What is the corresponding connection schematics?

[athershehzad]

I am using USB to TTL converter for debug UART and I have this directly to processor pins UART1_SIN and UART1_SOUT. 

Please see this link for reference https://www.adafruit.com/product/954 .

Connection detail is as follows.

Wire of Cable   Pin of T1042

GND                  GND

RX                      UART1_SOUT

TX                       UART_SIN

Power                  Not connected

[ufedor]

Provided problem description lacks technical details.

Please provide a digital scope trace showing all reset signals behaviour.

Also, what is the RCW source and does it contain a valid RCW?