HDLC packets are not coming from processor but line protocol is up

[suchitasharma]

Hello,

We are using T1040 based board and we are trying to send HDLC packets from our processor to cisco router via V.35 interface.

On cisco router line protocol is up but packets are not flowing from the processor. And it is not receiving the packets from cisco router also.

Log of cisco router:

Router#show interfaces serial 0/0
Serial0/0 is up, line protocol is up
Hardware is PowerQUICC Serial
Internet address is 10.100.100.30/24
MTU 1500 bytes, BW 1544 Kbit, DLY 20000 usec,
reliability 255/255, txload 1/255, rxload 1/255
Encapsulation HDLC, loopback not set
Keepalive set (32767 sec)
Last input never, output 00:00:03, output hang never
Last clearing of "show interface" counters 04:06:16
Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0
Queueing strategy: fifo
Output queue :0/40 (size/max)
5 minute input rate 0 bits/sec, 0 packets/sec
5 minute output rate 0 bits/sec, 0 packets/sec
0 packets input, 0 bytes, 0 no buffer
Received 0 broadcasts, 0 runts, 0 giants, 0 throttles
18 input errors, 0 CRC, 8 frame, 0 overrun, 0 ignored, 9 abort
36 packets output, 11628 bytes, 0 underruns
0 output errors, 0 collisions, 417 interface resets
0 output buffer failures, 0 output buffers swapped out
40 carrier transitions
DCD=up DSR=up DTR=up RTS=up CTS=up

Can u please suggest what we can do rectify this issue.

[r8070z]

I assume you run the nxp QorIQ Linux SDK based software. The nxp Linux SDK 2.0 provides ucc_hdlc driver. This driver routes HDLC frame to the T1040 TDM and require X-TDM-DS26522 card installed on the T1040RDB. The TDM-DS26522 drives the T1040 TDM bus clocks and syncs. ucc_hdlc can work in normal or loopback mode. You can see details in The QorIQ SDK V2.0-1703 Documentation. It is avaialable on
https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/linux-sdk...
For Verification in Linux it says:

1. After u-boot startup,set "qe-hdlc" parameter in hwconfig.

2. After bootup kernel, Kernel boot log for hdlc:
hdlc: HDLC support module revision 1.22

3. QE HDLC T1/E1 test
a. Make X-TDM-DS26522 card connected to T1040RDB board Slot.
b. To test tdm external ports, please plugin tdm t1/e1 loopback cable in the related port.
The following is HDLC port mapping with X-TDM-DS26522 card:
HDLCPort  X-TDM-DS26522 Port
Port A CH1;
Port B CH2;
c. HDLC test using E1.
Use the default dts to test E1 function. Test module can receive ucc_num as parameter. This number should be 1/3
related to the tdm port.
root@t1040rdb:~# mount /dev/mmcblk0 /mnt && cp /mnt/sethdlc ./sethdlc && ./sethdlc hdlc0
hdlc && \
192.168.0.1 hdlc0 && \
ping 192.168.0.2> ifconfig hdlc0 192.168.0.1 up && \
> route add -net 192.168.0.0 netmask 255.255.255.0 gw 192.168.0.1 hdlc0 && \
> ping 192.168.0.2
hdlc0: Carrier detected
PING 192.168.0.2 (192.168.0.2): 56 data bytes
Tx data skb->len:86
Transmitted data:
ff
44
45
00
00
54
cf
71
40
00
40
01
e9
e3
c0
a8
irq ucce:20000
TxBD: 1c00
Received data length:88
while entry times:0
Received data:
ff
44
45
00
00
54
cf
71
40
00
40
01
e9
e3
c0
a8
skb->protocol:800
irq ucce:80000

[suchitasharma]

Hi ,

      In our case , we are using FCC HDLC driver in NMSI mode .So, in that case tdm related changes and

    X-TDM-DS26522 device is not required . We have one transceiver SP505, which is connected to processor in one side  and another side cisco router is connected.

Is it possible that UCC hdlc work in standalone mode (NMSI ).

And also please find the attached diagram which is having the connection of our board with cisco router, which we are using for testing. TxCLK and RxCLK are shorted are we are using external clock CLK9 for TxCLK and CLK12 for RxCLK.

All the line protocol signals are up (DCD, DSR, DTR, RTS, CTS). But while probing TxD, we are not finding any data coming out from the processor.

Please suggest if we can do something for the issue.

[r8070z]

I think it is impossible that ucc hdlc work in standalone mode (NMSI ). The SDK document says: "The HDLC/TDM driver is implemented by UCC and TSA(HDLC is upper layer protocol of TDM)." Also device tree node for the ucc_hdlc has TDM specific values:

fsl,rx-sync-clock = "rsync_pin";
fsl,tx-sync-clock = "tsync_pin";
fsl,tx-timeslot = <0xfffffffe>;
fsl,rx-timeslot = <0xfffffffe>;
fsl,tdm-framer-type = "e1";
fsl,tdm-mode = "normal";
fsl,tdm-id = <0>;
fsl,siram-entry-id = <0>;
fsl,tdm-interface;

[suchitasharma]

Hi ,

      Thanks for the quick response. We have modified the device tree to make ucc work in hdlc mode .The modified device tree is given below:

ucc_hdlc: ucc@2000 {
compatible = "fsl,ucc_hdlc";
rx-clock-name = "clk12";
tx-clock-name = "brg2";
};

Please correct me if I m wrong .

[r8070z]

So it seems the HDLC driver without tdm parameters in the device tree does not connect UCC to the SI. It can be done by programming the QE registers. However  NMSI and TDM bus need for the same pins and these pins are configured in the RCW.

[suchitasharma]

Yes. We have done the same way as you said but internal loopback is working whereas hdlc driver tx and rx in normal mode is not working . could you please suggest what could be the reason for this?

[suchitasharma]

We are using T1040D4RDB board and using sethdlc utility to send HDLC packets.

Log of the commands that we are using for sending HDLC packets:

root@t1040d4rdb:~# sethdlc hdlc0 hdlc
fsl_ucc_hdlc.c ucc_hdlc_attach 982
root@t1040d4rdb:~# sethdlc hdlc0 cisco interval 10 timeout 25
fsl_ucc_hdlc.c ucc_hdlc_attach 982
root@t1040d4rdb:~# ifconfig hdlc0 10.100.100.15 up
hdlc0: Carrier detected
hdlc.c:76 hdlc_start_xmit()
Cisco HDLC for non ARP H/W
Tx data skb->len:22
Transmitted data:
8f
00
80
35
00
00
00
02
00
00
00
01
00
00
00
00
BD status value: 14000000
BD status value: 9c000016

[r8070z]

How are you trying to send HDLC packets from T1040 processor. Which T1040 based board? What software are you using?