The scheme is as follows. Events not masked in IM RxQD[RxFIntM, BSYIntM],
are forwarded to the FMFP_FCEV register selected by RxQD[FPMEVT_SEL],
which takes the format specified in T1024DPAARM, Section 5.13.22
These are write-one-to-clear bits. Further, if not masked in FMFP_CEE,
the request is forwarded to MPIC interrupt 80. See T1024DPAARM, Sections 5.7.3.8,
5.7.3.9, T1024RM, Table 5-1 and Section 24.3.73 for more information.
Have a great day,
Platon
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