DDR3L SDRAM interface input AC timing

[taslblr]

Hello NXP,

We are working on a Custom T2081 board, we are referring to the T2081 Datasheet (Document Number T2081 Rev. 3, 03/2018). I want to check the values of DDR3L SDRAM interface input and output AC timings below are the registers that are mentioned in the datasheet.

DDR3L SDRAM interface input AC Timings:

1. t CISKEW - Controller Skew for MDQS-MDQ/MECC
2. tDISKEW - Tolerated Skew for MDQS-MDQ/MECC

DDR3L SDRAM interface output AC Timings:

1. tMCK - MCK[n] cycle time
2. tDDKHAS - ADDR/CMD output setup with respect to MCK
3. tDDKHAX - ADDR/CMD output hold with respect to MCK
4. tDDKHMH - MCK to MDQS Skew
5. tDDKXDEYE - MDQ/MECC/MDM output Data eye
6. tDDKHMP - MDQS preamble
7. tDDKHME - MDQS postamble

My concern is, where I will be able to find these registers in the code and how I will configure them.

Please support/guide to the same.

Thanks and regards,
TASL Bangalore

[JosephAtNXP]

Dear TASL Bangalore,

The registers you found out in the T2081 datasheet can be found named and described in the T2081RM, particularly on the page 152.

Nonetheless, the way you can configure them is calibrating the memory, please use the QorlQ Configuration and Validation Suite. I indexed the QCVS DDR Tool User Guide so you can get introduced to the tool, this will set the phy registers for you when introducing all your DDR information.

Have a nice day. Best regards.