Core Time Base Clock Configuration (T2080, RCPM)

[bernhardsputh]

To whom it may concern,

I'm currently in the process of porting our RTOS to the T2080, to be precise the T2080RDB. While implementing the driver for the periodic ticker, for which I use the e6500-core's decrementer circuit (as every core will have it's own ticker), I stumbled across determining of the time base clock, the documentation [1] appears to be unclear with respect to what is happening inside the RCPM:

- Page 2315: RCPM_PCTBCKSELR selects the clock source for each core's time base. Which can either be the RTC clock or the Platform Clock divided by 16.

- Page 2316: RCPM_TBCLKDIVR provides the clock divider for the core time base. Which offers the divisions of 8, 16, 24,  or 32.

Unfortunately, the documentation does not show a diagram that shows the clock distribution / processing path inside the RCPM. Thus my question is whether the RCPM_TBCLKDIVR is always part of the equation? Thus if I select the Platform Clock /16 as time base clock, then this clock will at least be divided again by a factor of 8 by the RCPM_TBCLKDIVR, and thus the resulting time base clock I can get for the timer is Platform Clock / 128.

Best Regards

Bernhard Sputh

[1] QorIQ T2080 Reference Manual, Rev. 2, 02/2016

[ufedor]

The PCTBCKSELRL register have fields that will rout either the platform clock/16 or another clock signal called RTC (that can be supplied from GPIO1[14] pin of the chip) to the Core Timebase. Once the selection is done then we can decide if it is required to further divide the clock frequency by configuring TBCLKDIVR register.

You wrote:

> if I select the Platform Clock /16 as time base clock, then this clock will at least be divided again by a factor of 8 by

> the RCPM_TBCLKDIVR, and thus the resulting time base clock I can get for the timer is Platform Clock / 128.

Correct

[parth_gulati]

Hi,

How can I configure TBCLKDIVR as it is a read register.

I want to give my time base core as Platform clock/8 is it possible.