Failed to communicate with P3T1755 based on I3C bus
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Hello, I want to implement communication with P3T1755 based on I3C bus. At the current 12.5Mhz frequency, the FPGA sends a 7E/W broadcast command, and the slave device responds with an NACK. Could you please tell me what to do? I3C waveform diagram is as follows:
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The device is ACKing the first byte now. The ACK is the portion where the low level voltage is slightly above ground. I believe the issue is in your controller code. You need to generate an ACK_HOLD which keeps the ACK bit low after the rising edge of SCL. Our design is an FPGA based implementation. I am tasked with writing the C++ code that interfaces with the FPGA. The FPGA code is generated by a outside contractor and I do not have access to the Verilog source. The contractor told me that I had to set an ACK_HOLD bit in the command register for this type of access. After I did that, then it started to work. Before I set that bit, my waveform was similar to yours. The device ACKed, but released SDA on the rising edge of SCL.
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The first cycle with the Reserved Byte of 0x7E is open drain. I think you are clocking SCL too fast. When in open drain mode, reduce the clock to something like 400KHZ. I am working on the same part and it is ACKing me fine, but I clock it much slower. Check the datasheet, I think the top frequency is 3.4MHZ in push pull mode and then VCC must be greater than 1.8V. I don't have a scope attached. Only a simple logic analyzer. However, I uploaded a screenshot of this transaction. Notice that I can speed the clock up fast for the next byte which is the Common Command Code since it is push pull.
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Hello, I have tried again according to your suggestion. I dropped the SCL frequency to around 400Khz and the VCC to 3.3V. But the results are still not good. Have I missed anything else that needs attention? The waveform diagram is as follows: