FXLS8471Q—SPI Communication Question

[gaosonglin]

Hello !

I have some troubles to configure the SPI communication between FXLS8471Q and MPC5644A.

I need to confirm that the SPI Mode is waked up successfully by reading WHO_I_AM register(0x0D) , but I've got this stranger signal by reading the MISO pin with oscilloscope. I don't know what the meaning of this signal, and I want to ensure if the SPI mode had been waked up successfully. I found some people have asked same question,but he didn't say how to solve this problem. At the same time, I hope you can give me some advice to solve the problem.

Thanks!

MISO IS 00 00 00 NOT FF FF FF because the Vmiso is 3V not 5V, it test on MISO and the Header U4 is not tied to MISO2.

[gaosonglin]

i know what happed by some test , the MCU must set at this 

DspiCtar8471.B.DBR = DSPI_CTAR_BDR_NORMAL;
DspiCtar8471.B.FMSZ = DSPI_CTAR_FMSZ(8);
DspiCtar8471.B.CPOL = DSPI_CTAR_CPOL_LOW;
DspiCtar8471.B.CPHA = DSPI_CTAR_CAP_LEAD;
DspiCtar8471.B.LSBFE = DSPI_CTAR_MSB_FIRST;
DspiCtar8471.B.PCSSCK = DSPI_CTAR_PCSSCK_7;
DspiCtar8471.B.PASC = DSPI_CTAR_PASC_7;
DspiCtar8471.B.PDT = DSPI_CTAR_PDT_7;

i set the  CPHA as 1 at first , this question has been solved.

[TomasVaverka]

Hello Songlin,

OK, it was not clear from the first picture, I should have mentioned it. The FXLS8471Q indeed uses the ‘Mode 0′ SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the leading edge of clock signal and changed on the falling edge (CPHA = 0).

Best regards,

Tomas

[TomasVaverka]

Hello Songlin,

In order to select properly the SPI interface mode, you need to make sure that the SA0/MISO pin is floating (high-impedance) during power-up or when exiting reset. 

So if you cannot ensure that the SA0/MISO pin is floating during power-up, you can use later the RST pin (low - high - low) as soon as the MISO pin on your MCU is properly configured as high-impedance input.

Hope it helps!

Best regards,

Tomas