FXLS8471Q - FIFO Fill mode example code

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FXLS8471Q - FIFO Fill mode example code

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andrewneil
Contributor III

here:

https://community.nxp.com/t5/Sensors-Knowledge-Base/FXLS8471Q-FIFO-Fill-mode-example-code/ta-p/11080... 

by @TomasVaverka 

In the first code block, I think the comment against CTRL_REG4 is wrong (or, at least, misleading):

 

 

void FXLS8471Q_Init (void)
{
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x00); // Standby mode
  FXLS8471Q_WriteRegister(F_SETUP_REG, 0xA0); // FIFO Fill mode, 32 samples
  FXLS8471Q_WriteRegister(CTRL_REG4,   0x40); // Enable FIFO interrupt, push-pull, active low
  FXLS8471Q_WriteRegister(CTRL_REG5,   0x40); // Route the FIFO interrupt to INT1 - PTA5   
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x19); // ODR = 100Hz, Active mode
}

 

 

According to the datasheet, CTRL_REG4 contains only interrupt enable bits - not push-pull or active-low controls.

The push-pull and active-low controls are in CTRL_REG3  (the defaults are push-pull & active-low).

 

 

 

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Andrew,

Thank you again for your feedback, you are right, both the output mode (push-pull vs. open-drain) and polarity (active low vs. high) are configurable using bits pp_od and ipol in the CTRL_REG3 register.

I have updated the FXLS8471Q_Init function to make this clear.

void FXLS8471Q_Init (void)
{
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x00); // Standby mode
  FXLS8471Q_WriteRegister(F_SETUP_REG, 0xA0); // FIFO Fill mode, 32 samples
  FXLS8471Q_WriteRegister(CTRL_REG3,   0x00); // Push-pull, active low interrupt
  FXLS8471Q_WriteRegister(CTRL_REG4,   0x40); // Enable FIFO interrupt
  FXLS8471Q_WriteRegister(CTRL_REG5,   0x40); // Route the FIFO interrupt to INT1 - PTA5   
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x19); // ODR = 100Hz, Active mode
}

 

BR, Tomas

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Andrew,

Thank you again for your feedback, you are right, both the output mode (push-pull vs. open-drain) and polarity (active low vs. high) are configurable using bits pp_od and ipol in the CTRL_REG3 register.

I have updated the FXLS8471Q_Init function to make this clear.

void FXLS8471Q_Init (void)
{
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x00); // Standby mode
  FXLS8471Q_WriteRegister(F_SETUP_REG, 0xA0); // FIFO Fill mode, 32 samples
  FXLS8471Q_WriteRegister(CTRL_REG3,   0x00); // Push-pull, active low interrupt
  FXLS8471Q_WriteRegister(CTRL_REG4,   0x40); // Enable FIFO interrupt
  FXLS8471Q_WriteRegister(CTRL_REG5,   0x40); // Route the FIFO interrupt to INT1 - PTA5   
  FXLS8471Q_WriteRegister(CTRL_REG1,   0x19); // ODR = 100Hz, Active mode
}

 

BR, Tomas

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andrewneil
Contributor III

Thanks.

It would be useful to have some samples like this for the FXLS896xAF, please ...

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