Accelerometer FXLS896xAF - bug in library ?

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Accelerometer FXLS896xAF - bug in library ?

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adde_ado
Contributor III

Hi,

I'm testing the FXLS8964AF sensor on our custom board and I'm not getting any interrupts on INT1 when I configure my sensor for shake detection.

In a struct named gFxls896xafShakeConfig I have found the following comment but FXLS896xAF_INT_PIN_SEL_SDCD_OT_INT2_DIS is equal to 0x00. Is this a bug or have I missed something?

 

/* SDCD_WT_ENenabled for INT2 */

 

 

Our BT_MODE pin is connected to GND and my intention is to use  INT1 as our interrupt pin.

This is our register configuration (pretty much the same as it is explained in AN12004 on page 12):

Register      Data

0x15            0x00

0x15            0x02               FSR = 4 g and Standby mode

0x17            0x33               Wake ODR = 400 Hz and Sleep ODR = 400 Hz

0x2F            0x20               Enable X axis only for SDCD OT function

0x30            0xF0

0x31            0x04               Debounce time = 4 × (1/400) = 10 ms

0x33            0xFE

0x34            0xFA

0x35            0x02 

0x36            0x05

0x20            0xA0             Enabling DRDY_EN and SDCD_OT_EN

0x21            0x00              Routing DRDY interrupt to INT1 pin

0x15            0x03              FSR = 4 g and ACTIVE = 1

Best regards,

Adde

 

 

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AmitPurohit
NXP Employee
NXP Employee

Thanks Tomas.

Hi Adde,

FXLS896xAF_INT_PIN_SEL_SDCD_OT_INT2_DIS set to 0x00 configures INT1 pin for routing SDCD OT interrupt.

You can try following sensor configuration for shake detection:

Register Name

Offset

Value (to write)

Description

SENS_CONFIG1

0x15

0x02

FSR = +/-4g and Standby mode

SENS_CONFIG3

0x17

0x33

Wake ODR=400 Hz and Sleep ODR = 400 Hz

SENS_CONFIG4

0x18

0x21

Enable SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable and INT polarity set to high

SDCD_CONFIG1

0x2F

0x20

Enabling SDCD OT for X-axis

SDCD_CONFIG2

0x30

0xF0

Enable SDCD function, Enable Absolute Reference Mode and set OT Debounce counter to clear immediately when threshold criteria is false

SDCD_OT_DBCNT

0x31

0x04

Debounce time = 4 for transient detection

SDCD_LTHS_LSB

0x33

0xFF

Registers 33h and 34h set the OT LOWER threshold. In this example it is set to

hex2dec (FAFE) × 1.95 mg/LSB = -2.5 g.

SDCD_LTHS_MSB

0x34

0xFA

SDCD_UTHS_LSB

0x35

0x02

Registers 35h and 36h set the OT UPPER threshold. In this case it is set to

hex2dec (0502) × 1.95mg/LSB = +2.5 g

SDCD_UTHS_MSB

0x36

0x05

ASLP_COUNT_LSB

0x1E

0xFF

Registers 1Eh and 1Fh enable the ASLP function and set the sleep mode transition timer.

In this example it is set to hex2dec (07D0) × 2.5 ms (400 Hz Wake ODR) = 5 sec

ASLP_COUNT_MSB

0x1F

0x08

INT_EN

0x20

0x01

Enabling WAKE_OUT_EN

INT_PIN_SEL

0x21

0x00

Routing WAKE_OUT_EN interrupt to INT1 pin

SENS_CONFIG1

0x15

0x03

FSR = +/-4 g and ACTIVE = 1

 

Please try suggested sensor configuration.

Regards,

Amit Purohit.

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AmitPurohit
NXP Employee
NXP Employee

Thanks Tomas.

Hi Adde,

FXLS896xAF_INT_PIN_SEL_SDCD_OT_INT2_DIS set to 0x00 configures INT1 pin for routing SDCD OT interrupt.

You can try following sensor configuration for shake detection:

Register Name

Offset

Value (to write)

Description

SENS_CONFIG1

0x15

0x02

FSR = +/-4g and Standby mode

SENS_CONFIG3

0x17

0x33

Wake ODR=400 Hz and Sleep ODR = 400 Hz

SENS_CONFIG4

0x18

0x21

Enable SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable and INT polarity set to high

SDCD_CONFIG1

0x2F

0x20

Enabling SDCD OT for X-axis

SDCD_CONFIG2

0x30

0xF0

Enable SDCD function, Enable Absolute Reference Mode and set OT Debounce counter to clear immediately when threshold criteria is false

SDCD_OT_DBCNT

0x31

0x04

Debounce time = 4 for transient detection

SDCD_LTHS_LSB

0x33

0xFF

Registers 33h and 34h set the OT LOWER threshold. In this example it is set to

hex2dec (FAFE) × 1.95 mg/LSB = -2.5 g.

SDCD_LTHS_MSB

0x34

0xFA

SDCD_UTHS_LSB

0x35

0x02

Registers 35h and 36h set the OT UPPER threshold. In this case it is set to

hex2dec (0502) × 1.95mg/LSB = +2.5 g

SDCD_UTHS_MSB

0x36

0x05

ASLP_COUNT_LSB

0x1E

0xFF

Registers 1Eh and 1Fh enable the ASLP function and set the sleep mode transition timer.

In this example it is set to hex2dec (07D0) × 2.5 ms (400 Hz Wake ODR) = 5 sec

ASLP_COUNT_MSB

0x1F

0x08

INT_EN

0x20

0x01

Enabling WAKE_OUT_EN

INT_PIN_SEL

0x21

0x00

Routing WAKE_OUT_EN interrupt to INT1 pin

SENS_CONFIG1

0x15

0x03

FSR = +/-4 g and ACTIVE = 1

 

Please try suggested sensor configuration.

Regards,

Amit Purohit.

1,384 Views
TomasVaverka
NXP TechSupport
NXP TechSupport

@AmitPurohit - can you please look into it and comment?

Thanks & Regards,

Tomas