Hi Safety team,
We have a major mm customer using the S32K341/311, and have asked additional Safety Manual questions. They are developing both ASIL B and ASIL D applications:
Q1: For AOU_GEN_FOLLOW_ARM_M7_DOC, can you confirm the text "this chip's Safety Manual" is referring to the Arm Cortex-M7 Safety Manual or the safety manual of the S32K3xx?
Q2: What is comm safe prot (like in SM4.COMM_SAFEPROT)? Customer cannot find information about this.
Q3: Is it possible to clarify which SMs and AoU are exclusive to ASIL D, and which are also necessary for ASIL B?
Q4: The documentation for SM2 shows that SAF mechanisms are relevant for variant S32K311, which is ASIL B. Why is SAF needed for this chip if SAF is targeting ASIL D only?
Q5: The documentation for SM2 shows that SAF mechanisms bring DC of associated failure modes to 90%. What happens if these SAF mechanisms, DC goes down to 60% (acceptable for ASIL B) or 0% (which would be a gap for ASIL B)?
Thanks!
