QFN32 pin terminal open/short test results

[hiroyuki_murako]

Hello, I am using the S32K116 QFN32 pin.

Could you please give me the test results of the open/short test of the terminal of the QFN32 pin?

Potential Failure Mode
　Pin Open
　Pin Shorted to Ground
　Pin Shorted to adjacent pin (N+1)
　Pin Shorted to Vdd (5V)

S32K116_32qfn	Pin Name	DEFAULT
3	VDD	VDD
4	VSS	VSS
5	PTB7	EXTAL
6	PTB6	XTAL
20	VSS	VSS
21	VDD	VDD
28	PTA10	JTAG_TDO
29	PTC5	JTAG_TDI
30	PTC4	JTAG_TCLK/SWD_CLK
31	PTA5	RESET_b
32	PTA4	JTAG_TMS/SWD_DIO

[Yashwant_Singh · Accepted solution]

Hi Hiroyuki,

1. The JTAG and Reset pins are not modelled explicitly in the FMEDA. 

2. The VDD and VSS pins are modelled in the FMEDA and their Failure modes can be seen in the static version under the name of "Package Contacts"

3. NXP's assumed safety concept recommends not to use XOSC as the system clock source and instead use FIRC. (see the attached Safety Manual Snippet). Therefore the XOSC (and hence its package contacts) are marked NSR in the FMEDA and so not reflected in the Static version of the Clock FMEDA. 

Hope this helps!

Thanks!

-Yashwant.

[hiroyuki_murako]

Dear Yashwant,

Thank you very much for your notice and support.
I was able to understand the content.

Thanks!