MPC5746 over-voltage failure effects

[allanwatson]

Hello All - 

We are conducting our dependent failure analyses and are looking for information on the effects of over-voltage on the MPC5746B.  Is there any reference material stating the failure modes and failure mode probability distribution when the micro is subject to an over-voltage condition?

The FMEDA information and safety manual only appear to consider operation within the rated voltage range.

Specifically we are looking for:  What is the failure rate for an output pin (e.g., from eMIOS or GPIO) becoming active (either high or low), independent of core control or even if the RST pin is asserted, if any of VDD or 3V3 supply rails are above the input rating for the micro?

That is - given VDD_HV(5V) > limit and/or VDD_LV(1.2V) > limit, what is the probability that an output pin will randomly turn on?  If this is a function of the input voltage, is there data of how that probability changes with voltage?

We'd like to have data for distribution of fail high, fail high-z, and fail low.

Thanks and regards,

[jehoda_refaeli]

Hello Allan,

Thank you for your question. 

Technically speaking, there is no failure of the micro up to the absolute maximum rating specification, however, AC and DC specifications are guaranteed only up to the DC specifications mentioned in the electrical specification.

Given that the MCU doesn't generate I/O supplies, the FIT rate would be 0. If the power management has a defined over voltage, you can carry that directly to failure of the MCU (Lambda(EOS) - Electrical Over Stress).

W.R.T. I/O - Given that the design is verified and tested with sufficient process margins, the failure, if exist, will depend on level shifter behavior compared to ratio of core supply to I/O supply and additional process variation and temperature at which the over voltage happened. These are beyond analytical analysis.

Best Regards,

Jehoda Refaeli

BL AMP Lead Functional Safety HW Architecture