Cobra-55 and eTPU: integrity of shared data access

[lucabarbiero]

Hello,

I have a motor control application based on the Cobra-55/MPC5777C, which uses the eTPU engines to allocate motor control functions. The context is that of aerospace and DO178-C DAL A, which is comparable to automotive ASIL-D.

I am concerned with the integrity of eTPU shared data memory access from the CPU (I am using only one core, the one in lockstep). The software running on the CPU is not synchronized with the software running on the eTPUs.

How can I make sure that eTPU shared data is accessed safely in read/write by both CPU and eTPU?

I would like to avoid having the eTPU functions to send interrupts to the CPU every time data is ready to be transferred to/from the eTPU shared data memory. In general, I would like to have no (or low) control coupling between CPU and eTPU.

Another option would be DMA transfers initiated by eTPU functions, but how can I make sure that transferred data is only accessed once the transfers have been completed? And of course, I know that the DMA controller cannot be trusted upon, transferred data must be checked for consistency by software.

What are the options I have with the Cobra-55?

Thanks in advance for any support!

[sandeepkumarbom]

Hi,

There are multiple ways how to ensure data coherency. Coherency between eTPU engines (A and B) can be ensured by the use of HW semaphores. But this needs to be implemented in the eTPU source code. Host (CPU) and eTPU coherency can be ensured by the use of SW semaphores - also needs SW changes. To read two consecutive parameters from eTPU SPRAM there can be used CDC = coherent dual parameter Controller

Please let us know if you have eTPU compiler and our source codes or writing your own code?. NXP provides binary downloaded from the web and the resolver functions have both HW and SW semaphores mechanism already implemented.

For more info regarding coherency, please refer to eTPU RM Chapter 1.5.4 Parameter Sharing and Coherency

Thanks,

Sandeep