I am running some test code on S32Z270 RTU0 core 0 (R52) with RTU0_CORE_CLK set to 1GHz where the execution time seems to too long. In comparison I am running the same code on SS32K388 core 0 (CM7) with core clock set 320MHz. Given the clock frequency increase I would have expected some faster execution but instead the execution time is longer.
Build/compilation flags are held identical for both binaries (see attached txt file buildinfo.h)
(1) Since the clock configuration in the S32 Configuration Tool is kind of sophisticated for the S32Z how can I make sure the RTU0 core 0 clock frequency is 1GHz as intended?
I have routed out the RTU0_CORE_DIV2_CLK via MC_CGM_3_MUX4_CSC (e.g., SEL_CTL = 0x3D) to CLKOUT_4 (PAD_040 of BGA594) including a divider of 10 in MC_CGM_3_MUX4_DC_0 (e.g., DIV = 0x9). See also attached register readings. If I measure 50MHz at CLKOUT_4, can I presume that (a) RTU0_CORE_DIV2_CLK is 500MHz and (b) RTU0_CORE_CLK is 1GHz?
(2) I have measured the execution time of pin writes to GPIO using S32Z RTD2.0.1 and measuring high/low times of scope channel CH5 - TESTFLAG which is roughly 3.4us. Is there the possibility that you could confirm whether they seem to be alright or too slow?
(3) I am not sure what I am missing.
Hi,DirkEtzler
Sorry for the reply late.
(1) I have routed out the RTU0_CORE_DIV2_CLK via MC_CGM_3_MUX4_CSC (e.g., SEL_CTL = 0x3D) to CLKOUT_4 (PAD_040 of BGA594) including a divider of 10 in MC_CGM_3_MUX4_DC_0 (e.g., DIV = 0x9). See also attached register readings. If I measure 50MHz at CLKOUT_4, can I presume that (a) RTU0_CORE_DIV2_CLK is 500MHz and (b) RTU0_CORE_CLK is 1GHz?
>>>About this question, the number 7 is assigned to RTU0_CORE_DIV2_CLK, you also should program GPR3.CLKOUT4SE to set this value. Could you try to confirm if you have set this register?
BR
Joey
Hello @Joey_z,
thanks for the quick reply. Please see below my answers to the questions:
1) I am using a combination of the S32Z2XX motherboard + S32Z2XX daughterboard.
a) S32ZXX motherboard X-S32X-MB version A
b) S32ZXX daughterboard SCH-50588 REV B2 / 700-50588 REV A2
2) Code is compiled and linked using S32DS Version 3.6.7 Build 260420. There is no change when using previous releases of the S32DS such as Version 3.6.6 or 3.6.5. I am using RTD2.0.1 for S32Z2XX.
3) I will send a copy of the project using DM.
Attached is also a photo of the package markings.
