S32M276 - Constant 1s reset Loop (MCU_HSE_SWT_RST_RESET) using RTD 6.0.0

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S32M276 - Constant 1s reset Loop (MCU_HSE_SWT_RST_RESET) using RTD 6.0.0

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Hi,
We are experiencing a continuous reset loop on both a custom board based on the S32M276 and in the official NXP development board using RTD 6.0.0.

Observed Behavior:
When the JTAG debugger is connected, the application runs correctly without any unexpected resets.
Upon reconnecting the debugger and inspecting the reset reason via the MCU/RGM status registers, the reset cause is identified as: MCU_HSE_SWT_RST_RESET.


The reset counter associated with the HSE Watchdog (HSE_WDT) increments after every cycle.

After disconnecting the debugger and doing a power cycle the device enters a reset loop approximately every 1 second.


Current Configuration:
    MCU: S32M276
    RTD Version: 6.0.0

- Could you please clarify the specific trigger for MCU_HSE_SWT_RST_RESET?
- What is the recommended procedure in RTD 6.0.0 to either disable this HSE-managed reset or properly service the WDT?

 

Thanks

- Miguel Marquez

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1 Solution
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The solution was to prescale the HSE Clock from 120MHz to 60MHz. 

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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @Miguel_Marquez_Schaeffler,

Thank you for the detailed explanation, along with the additional debug information.

From your description, this sounds like a clock configuration issue. Usually, this behavior happens when clock ratios are not followed: [s32k312]Read reset reason by RTD function, HSE_SWT_RST is occurred after a functional reset. - NXP ...

Could you please confirm you've followed the clocking modes as detailed in chapter 21.7.2 from the S32M27XRM? Specifically, check HSE_CLK configuration: Solved: S32K312 flexcan example not running on Power reset - NXP Community.

Best regards,
Julián

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After further research on the forums we believe this information might be useful to debug the issue: (This is with the debugger connected)

 

UT0 REGISTER VALUE

Miguel_Marquez_Schaeffler_0-1776194807760.png

DCMUTS VALUE

Miguel_Marquez_Schaeffler_1-1776194830840.png

UTEST MEMORY START: 

Miguel_Marquez_Schaeffler_2-1776194844252.png

 

 

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The solution was to prescale the HSE Clock from 120MHz to 60MHz. 

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