s32k144 pwm deadtime setting issue

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s32k144 pwm deadtime setting issue

3,123 Views
alice_th
Contributor III

hello @danielmartynek 

when i set with dead time, ch1 don't have waveform output, could you help to check it 

alice_thanks_0-1728544749957.pngalice_thanks_1-1728544765401.png

 

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3,065 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@alice_thanks

I opened your project and you can see that our IDE has prompted you with a configuration error.

Senlent_0-1728615816321.png

you should disable this options as you have already enable ch1

Senlent_1-1728615906461.png

 

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3,052 Views
alice_th
Contributor III

@Senlent hello,

i have question about it, i need below waveform, as my understanding,

i need enable channel(n+1) output with deadtime setting with duplicate channel(n) 

alice_thanks_0-1728627321258.png

if disable it , how can achieve it ?

or can you help modify the project , thnaks !

 

 

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2,969 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@alice_thanks

Your duplicate question has already been answered here.

https://community.nxp.com/t5/S32K/about-s32k144-pwm-phase-shift/m-p/1972514/highlight/false#M41973

 

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3,048 Views
alice_th
Contributor III
with duplicate channel(n) or invert channel(n)
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3,041 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@alice_thanks

You can find "ftm_combined_pwm_s32k144" in S32 DS, please refer to it.

 

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3,024 Views
alice_th
Contributor III

hello @Senlent 

i just set larger deadtime, i see the delay, for combined it only support invert waveform, how to generate duplicate channel(n+1) ?

and the combined  only support Adjacent channel, if i need with ch0, and duplicate/invert channel 3 or channel6  with deadtime setting.

another question: is there phase shift example base on this sdk ?

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3,019 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@alice_thanks

You need to read our data sheet or AN5303

The FTM module of S32K1 supports complementary mode, which is enabled by the COMP bit in the FTM_COMBINE register. The output signal is generated only by the even-numbered FTM channels, and the odd-numbered channels are generated by complementary logic as a supplement to the even-numbered FTM channels. A separate complementary PWM can be output for each pair of FTM channels.

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2,982 Views
alice_th
Contributor III

@Senlent 

i tested the AN code, have some questions about it

void Phase_Shifted_PWM()
{
SCG_Init();
HSRUN_Init();
    /* Enable clock for FTM1 */
    PCC->PCCn[PCC_FTM1_INDEX] = PCC_PCCn_PCS(6) | PCC_PCCn_CGC_MASK;
    /* Enable clock for PORTB */
    PCC->PCCn[PCC_PORTB_INDEX] = PCC_PCCn_CGC_MASK;
    /* Enable clock for PORTD */
    PCC->PCCn[PCC_PORTD_INDEX] = PCC_PCCn_CGC_MASK;
 
    PORTB->PCR[2] = PORT_PCR_MUX(2); // Set PTB2 for FTM1 � Channel0
    PORTB->PCR[3] = PORT_PCR_MUX(2); // Set PTB3 for FTM1 � Channel1
    PORTD->PCR[8] = PORT_PCR_MUX(6); // Set PTD8 for FTM1 � Channel4
    PORTD->PCR[9] = PORT_PCR_MUX(6); // Set PTd9 for FTM1 � Channel5
 
    /* Enable combine, complementary mode and dead-time for channel pair CH0/CH1 and CH4/CH5 */
    FTM1->COMBINE = FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_DTEN0_MASK
          | FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_DTEN2_MASK;
 
    FTM1->CONTROLS[0].CnSC=FTM_CnSC_ELSB_MASK; // Select high-true pulses
    FTM1->CONTROLS[1].CnSC=FTM_CnSC_ELSB_MASK; // Select high-true pulses
    FTM1->CONTROLS[4].CnSC=FTM_CnSC_ELSB_MASK; // Select high-true pulses
    FTM1->CONTROLS[5].CnSC=FTM_CnSC_ELSB_MASK; // Select high-true pulses
 
    /* Set Modulo (10kHz PWM frequency @112MHz system clock) */
    FTM1->MOD = FTM_MOD_MOD(11200-1); // Set modulo
    FTM1->CONTROLS[0].CnV=FTM_CnV_VAL(2800); // Set channel Value
    FTM1->CONTROLS[1].CnV=FTM_CnV_VAL(8400); // Set channel Value
    FTM1->CONTROLS[4].CnV=FTM_CnV_VAL(5600); // Set channel Value
    FTM1->CONTROLS[5].CnV=FTM_CnV_VAL(11200); // Set channel Value
    FTM1->CNT = 0;         // Counter reset
/* Insert DeadTime (1us) */
FTM1->DEADTIME = FTM_DEADTIME_DTPS(3) | FTM_DEADTIME_DTVAL(7);
    FTM1->SC|=FTM_SC_CLKS(1)|FTM_SC_PWMEN0_MASK|FTM_SC_PWMEN1_MASK|FTM_SC_PWMEN4_MASK
        |FTM_SC_PWMEN5_MASK; // Select clock and enable PWM
 
    while(1);
}
which part is phase shift setting ?
 
CnV i think is  duty cycle , 2800 25% 8400 75% duty cycle, why waveform is 50% duty cycle
alice_thanks_0-1728716094137.png

 

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3,016 Views
alice_th
Contributor III

hello @Senlent 

i see the AN you mention, it's all register setting for it, does the tools support it ? do you have api to do this ?

does the sdk have api or how to use the tools to set for the phase shift example ?

can you help with phase shift example with the SDK ?

 

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3,070 Views
alice_th
Contributor III

when disable dead time setting , both ch0 ch1 have waveform output,

for ch1 there is nothing change, could you please help check the project i have already attached ?

alice_thanks_0-1728612488670.png

 

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