Hi @rlaxortn,
1. & 2. Yes. It's better to manage the cache coherency so the CPU does not read stale data. You can refer to the C40_Ip_Example provided by the RTD package; it shows how to initialize the driver, clear the sectors before E/W, and reads the data.

Also, you can refer to chapter 4.1.55 (Parameter MemSynchronizeCache) from RTD_MEM_43_INFLS_UM.pdf (MCAL layer of C40_Ip driver):
...\S32DS\software\PlatformSDK_S32K3\RTD\Mem_43_INFLS_TS_T40D34M60I0R0\doc\
3. A/B swap is HW assisted, managed by HSE firmware. When OTA is enabled in the part, device flash is divided in 2 blocks.
- Active block, where the application code is located.
- Passive blocks, where the rollback image is located
You can find some information in the previous links I've shared, as well as this presentation: S32K3 OTA AB SWAP DEMOSTRATION.
There is also the Unified bootloader Demo, which is a UDS bootloader solution for S32K3xx, however it is provided as is with no further support.
Best regards,
Julián