eFlexPWM waveform generation issue

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eFlexPWM waveform generation issue

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xingyun
Contributor II

I want to achieve 6-channel PWM complementary wave generation, but with the following configuration, even though all 6 pins on the chip are connected, there is no waveform output.
After enabling PWM, the output on the board is completely noise-free. Could you please help me identify where my problem lies? Thank you all very much.

I don't know why the images won't display. Let me first describe my configuration.

The PwmChannel has 3 sub-channels (0/1/2). The Clock Source Selection in the FlexPwmSubModules is all set to FLEXPWM_IP_CLKSOURCE_PERIPHERAL_CLK. Initialization Control Selection are MASTER_RELOAD, MASTER_SYNC, and MASTER_SYNC respectively. Reload Source Selection and Force Source Selection are both set to MASTER.

In each Sub, there is only the PWMA (Phase-Weighted Magnitude) and the edge-symmetric mode.

In each Sub, there is only PWMA (Phase-Weighted Magnitude) and the edge-symmetric mode. Channel Output in fault, stop, and debug modes is LOGIC_0. In the "FaultSettings", select all options from 0 to 3. The Fault Level of Fault0 to Fault3 is all at LOW.

Please help me figure out why no waves are generated at the chip area.

 

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3 Replies

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

I can recommend to start with available "FlexPWM_Pwm_Ip_Example_S32K396" RTD demo example. It show FlexPWM independent configuration on single submodule, but you can easily modify it to complementary functionality on several submodules. This is a setting I used to modify add submodules 0 and 1 to generate complimentary signals on its PWMA/PWMB outputs. image.pngimage.png

image.png

Below is respective output signals after FlexPwm_Ip_Init is called

image.png

image.png

You can add another pins and submodule and set it accordingly to submodule 1

Hope it helps.

BR, Petr

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800 Views
xingyun
Contributor II

Thank you very much for your reply. I am now able to send waves. However, there is still one issue at present. My Default Period is 16000, the clock CORE_CLK is 160 MHz, and it is in the edge-triggered mode. I wanted to obtain a PWM with a frequency of 10K, but what I actually got was 2.4KHz.

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794 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

I do not see issue here. With setting 

 
 
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