How can start the VLRUN Mode ?
Normaly the MCU start with FIRC after reset. Now I want to change from Run Mode with FIRC to VLRUN Mode with SIRC after reset.
I saw in the ref that the RCM_SRIE Register is responsible for this:
How do I use this correctly?
I tried a which is still not working at the Moment:
/* Shut down Fast IRC and transit to VLRUN-Mode*/
RCM->SRIE = RCM_SRIE_DELAY(0); /*Reset Delay Time --> 0 10 LPO cycles */
RCM->SRIE = RCM_SRIE_SW(1); /* Software Interrupt --> 1 Interrupt enabled */
/* initiate Slow IRC Clock */
/* Slow IRC Configuration Register (SCG_SIRCCFG) */
SCG->SIRCCFG = SCG_SIRCCFG_RANGE(0); /* 0 Slow IRC low range clock (2 MHz) */
/* Slow IRC Control Status Register (SCG_SIRCCSR) */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCSEL(1); /* 1 Slow IRC is the system clock source */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCVLD(1); /* 1 Slow IRC is enabled and output clock is valid */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCLPEN(1); /* 1 Slow IRC in VLRUN-Mode is enabled */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN(1); /* 1 Slow IRC is enabled */
/* Slow IRC Divide Register (SCG_SIRCDIV) */
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(8); /* SET FIRDIV1_CLK to SIRC/4 = 2 MHz */
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(8); /* SET FIRDIV2_CLK to SIRC/4 = 2 MHz */
SCG->VCCR = SCG_VCCR_SCS(2) /* SIRC as clock source */
| SCG_VCCR_DIVCORE(2) /* DIVCORE=2, div. by 2: Core clock = 2/2 MHz = 1 MHz */
| SCG_VCCR_DIVBUS(2) /* DIVBUS=2, div. by 2: bus clock = 2/2 MHz = 1 Mhz*/
| SCG_VCCR_DIVSLOW(2); /* DIVSLOW=2, div. by2: SCG slow, flash clock= 1 MHz*/
if((SCG->CSR & SCG_CSR_SCS_MASK >> SCG_CSR_SCS_SHIFT) != 2)
} /* wait for sys clk src = SIRC */
I think the Fast IRC will be always selected as default in RUN mode out of reset.
The chapter 26.1.3 of the Reference manual deals with disabling Fast IRC in RUN mode before entering VLPR.
Note, in your code, you write to read-only bits SIRCVLD, SIRCSEL.
I have made a few changes in your code. You can find it attached.