Why FlexCAN init stops while clearing RAMn?

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Why FlexCAN init stops while clearing RAMn?

971 Views
dasitor
Contributor II

Hello,

I am new to the NXP S32K144. I am trying to develop an application that uses all 3 CAN modules at the same time. I run without any problem the example "FlexCAN_s32k144", which uses CAN 0. We are using a custom board with access to the three CAN modules (through transducers, of course). When I try to run the same example code just changing "CAN0" for "CAN1" or "CAN2", the init procedure stops at the RAMn clearing loop. For the moment I am trying to get each CAN module to work by itself, and all the code referring to the other modules is commented out. The PORTs are configured just before calling the init routine, but I have also tried to reverse the order without success. This is the code I am using (basically the same as in the example):

// START OF CODE

void FLEXCAN1_init() {

    uint32_t    i = 0;

    PCC->PCCn[PCC_FlexCAN1_INDEX] |= PCC_PCCn_CGC_MASK;    // CGC=1: enable clock to FlexCAN0
    CAN1->MCR |= CAN_MCR_MDIS_MASK;                                // MDIS=1: Disable module before selecting clock
    CAN1->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK;                        // CLKSRC=0: Clock Source = oscillator (8 MHz)
    CAN1->MCR &= ~CAN_MCR_MDIS_MASK;                                // MDIS=0; Enable module config. (Sets FRZ, HALT)
    /* Good practice: wait for FRZACK=1 on freeze mode entry/exit: */
    while (!((CAN1->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}

    /* Configure timing parameters: */
    CAN1->CTRL1 = 0x00490002; // CHANGE: Configured for 1MHz instead of 500KHz

    for(i=0; i<128; i++ ) {        // CAN1: clear 32 msg bufs x 4 words/msg buf = 128 words
            CAN1->RAMn[i] = 0;    // Clear msg buf word
    }

// EXECUTION NEVER REACHES THIS POINT <-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-<-

    /* Message filters initialization: */
    for(i=0; i<16; i++ ) {    // In FRZ mode, init CAN1 16 msg buf filters
            CAN1->RXIMR[i] = 0xFFFFFFFF;
    }
    CAN1->RXMGMASK = 0x1FFFFFFF;

    /* Configure Message Buffer #4 for reception -- Word 0: */
    CAN1->RAMn[ 4*4+ 0] = 0x04000000;
    /* Configure Message Buffer #4 for reception -- Word 1: */
    CAN1->RAMn[ 4*4+ 1] = 0x14440000;

    /* Configure FlexCAN module: */
    CAN1->MCR = 0x0000001F;

    /* Good practice: wait for FRZACK to clear (not in freeze mode): */
    while ((CAN1->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)  {}
    /* Good practice: wait for NOTRDY to clear (module ready):  */
    while ((CAN1->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)  {}
}

// END OF CODE

When I stop the debugger, it seems that a "default_isr" is executing, so I tend to think that there is a problem accessing the RAM assigned to CAN1 and CAN2, but I really don't know. Where should I look?

Thanks in advance!

2 Replies

741 Views
alexandrunan
NXP Employee
NXP Employee

Be aware that the FLEXCAN1 and FLEXCAN2 have only 16 MBs so you need to clear only 16x4 = 64 

for(i=0; i<64; i++ ) {        // CAN1: clear 16 msg bufs x 4 words/msg buf = 64 words
            CAN1->RAMn[i] = 0;    // Clear msg buf word
    }

BR,

Alexandru Nan

741 Views
dasitor
Contributor II

Yes, that was it. I have run the modified code and now it works. Many thanks!

As a reference, I should mention that I have found that info in table 53.1, section 53.1.1 of the Reference Manual.

Thanks again!

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