The SPI Always report a fault

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The SPI Always report a fault

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chenyh
Contributor II

I used the SPI of S32K312 to communicate with BE13.When I read data through BE13, BE13 always replied to me that SPI was faulty, and the fault was that a clock was missing during the first SPI communication. I checked the waveform with an oscilloscope and found that there was no clock signal missing during the first SPI communication, so I would like to ask, Is my SPI not configured or is it incorrectly configured? I hope you can reply to me sometime.Here is my configuration and code diagram.Thinks.ab067e3b0c2fd07855b8e24e523f35c.png95d24fe91d11af62129107d38fccb34.png683bc0d1c57eb9f2fc146064a892874.png

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chenyh
Contributor II

These two are the SPI timing and clock phase and polarity of the BE13, and the SPI clock is 60MHZa5acbd440bae332c48a1efcb0df652e.png369a477809f8154bcb12a72f0cec1ae.png

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IsaulO
NXP Employee
NXP Employee

Hi @chenyh,

We have tested your configurations and observed that the clock frequency is set to 200kHz.

IsaulO_1-1733953528517.png

Based on the image shared, we can see that the minimum SPI Frequency supported by your BE13 is 0.5MHz.


Additionally, we notice that you are using half-duplex transmission but have not configured the SpiDeviceHalfDuplexSupport. We suggest reviewing these configurations.

IsaulO_2-1733953565170.png

Hope it helps you.

Have a nice day!
IsaulO.

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chenyh
Contributor II
I use full duplex, it's still the same problem, I read The manual for BE13."The SPI command is composed of 32 SCLK cycles. When receiving data, the MOSI line is latched on the rising edge of each SCLK pulse.
The number of clock cycles occurring on the SCLK pin while the CSB pin is asserted low must be 32. The serial output data is available
on the rising edge of SCLK, and transitions on the falling edge of SCLK. The content of MISO reported by the 900719 depends on the
previous selected register address." But I used the word TRAILING, which I think should mean trailing on the second edge, and when I used that, the data collection was all right, except for BE13, which told me that my clock was missing, If I use "LEADING", the data I receive are all wrong, and my current "SpiBaudrate" is 1,000,000. Therefore, according to the " TRAILING" I used, there are indeed 31 clocks, but the data are all correct, while the use of "LEADING" is wrong. Could you please give me a reply?
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IsaulO
NXP Employee
NXP Employee

Hi,

Based on your comments and the image shared about BE13 manual, the data is latched on rising edge of each SCLK pulse. This indicate that the SPI mode could be 0 or 3.
If you are using Trailing Edge, you need to set CPOL=1 to ensure the requirements of the BE13.

IsaulO_4-1734116179017.png

IsaulO_5-1734116184619.png

If you are using Leading Edge, you need to set CPOL=0 to ensure the requirements of the BE13.

IsaulO_6-1734116211534.png

IsaulO_7-1734116217811.png


Note: These recommend options are based just on your comments and the image shared, we suggest check the BE13 manual.

Additionally, it is helpful to examine the data frame to check inconsistencies during the process. If you can share the data frame or clock signals, I can help visualize and analyze any potential issues.

Have a nice day!
IsaulO.

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chenyh
Contributor II

07adfff397a1bb6dc568d4612ebcc85.png34b125379beae46102e81fe0fc42712.pngUse half duplex mode must check the 'SpiDeviceHalfDuplexsupport'? Now I can communicate through half duplex, is it because I have checked 'SpiHalfDuplexModeSupport'?If I checked SpiDeviceHalfDuplexsupport, can you give me an example of send and receive, BE13 communication must be sent and I sent 32 bit at a time, 4 bytes of data,Looking forward to your reply

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