Setup XRDC domains and assign by PID for S32K344

[oskarjohansson]

Hi, I'm trying to setup a safe context in the S32K344 and control the memory and peripheral access based on the PID. Simplified I want to create two "process", one safe/secure that has access to some part of the memory/peripheral and one non-safe that doesn't have access to some part of the memory/peripherals. I'm looking at the XRDC module and try to configure, but you are restricted to assign one domain per master instance? 

So is it not possible to have different access levels for one core based on the PID?

Best regards,

Oskar

[davidtosenovjan]

It can be done, one core master can be assigned to multiple domains.

[oskarjohansson]

Thank you for your reply, but when I look at the MDA_Wn_m_DFMT0, for the core master, there is only one MDA_W0_0_DFMT0? Or is it something I miss here?

Not as in the example where a master 4 here has 4 domains (?)

If I try to setup the XRDC in the S32DS and try to add another configuration in the Domain Assignment I only get:

Best regards,

Oskar

[davidtosenovjan]

This is one domain (0) and by '+' you can add another domain (1-3). All can use multiple core masters.

[oskarjohansson]

Yes, but when I do that and add the same core master (Xrdc_0_CM7_0) twice I get the error message above.

So it is possible to add multiple core master to a defined domain, but not one core master to multiple domains that will changed based on the PID register? 

Best regards,

Oskar

[davidtosenovjan]

Yes, you are right.

You may have multiple masters in one domain every master must be in different one.

For instance for S32K388, you may have CM7_0,CM7_1 and CM7_2 in Domain 0 and CM7_3 in Domain 1.

[oskarjohansson]

Okay, so just to clarify, in order to achieve "Isolation of safety-critical and non-safety-critical code" it is necessary to have a processor that has two cores that can run in their own domain, as it is not possible to assign one core to different domains. 

So for the S32K344, a 2-core lockstep, it is not possible to use the XRDC to create different domains for the core to create an isolation between the safety and non-safety code? It would be necessary to use something like the S32K358, which has a 2-core lockstep and an additional single core?

Best regards,

Oskar

[davidtosenovjan · Accepted solution]

Yes, I would agree with that.