Setting S32K144 RUN mode to 80Mhz in Processor Expert

[mnewton]

In S32DS_ARM_v2.2 and S32SDK_S32K1xx_RTM_3.0.0 Processor Expert I am trying to set RUN mode to 80MHz

However if I set System PLL Multiplier to x20, I get a warning in PE that -

Warning: The resulting SPLL_CLK frequency must be between 90 and 160 MHz (System PLL Multiplier)

How do I configure a RUN mode of 80Mhz under PE?

[Robin_Shen · Accepted solution]

Hi mnewton,

According to the "Table 34. SPLL electrical specifications", the FSPLL_CLK PLL output frequency 90 — 160 MHz.

So please configure the SPLL to 160MHz, and then select SYS_CLK to 80MHz(SPLL_CLK/2).

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[mnewton]

Many thanks for the solution - apologies I focussed on the '90Mhz' and overlooked the other end of the scale at 160MHz and the divide by 2 now obvious usage!

While I have reviewed AN5425 I am finding 5.1 HSRUN mode entry slightly ambiguous, especially when used with the PE / SDK.

Do I need to create another clockMan1_InitConfig1 with a different SPLL and divider, and add it to the CLOCK_SYS_Init() clock_manager_user_config_t array?

Then to enter HSRUN mode call

POWER_SYS_SetMode(HSRUN, POWER_MANAGER_POLICY_AGREEMENT);

CLOCK_SYS_UpdateConfiguration(1U, CLOCK_MANAGER_POLICY_AGREEMENT);

and then reverse the process on exit? Or should I be adding the CLOCK_SYS_UpdateConfiguration as callbacks in the Power_sys management?

Is there an Application note or guide to switching between 80MHz RUN mode and 112MHz HSRUN mode with the SDK - the example power_mode_switch_s32k14x only shows the simpler case of switching from 48MHz FIRC clock to 112MHz SPLL clock ?