SWOCTRL and OUTMASK register update for BLDC Motor Control

[Qazi]

I am using the following configuration to update SWOCTRL and OUTMASK registers using Software trigger.
What I have come to understand by reading Reference manual and application manuls is that with PWM enhanced synchronization, the registers can be updated at loading point which I expect to be End of a Time period of PWM. But what I have observed is that the registers are updated as soon as software trigger is set to HIGH. 
In one applicaiton manual, i also read which confused me and hence my question, is the concept of loading point is that an at of PWM an ISR is called and we update the registers over there rather than we change the registers at an arbitrary location and they are updated at the end of PWM.

Please let me know if there is anything unclear in the question. I am attaching the following picture. The Yellow signal shows where the ISR started, the Green line goes LOW where the software trigger is set. Phase Switch is a point when Blue signal goes LOW, and the Pink signal goes HIGH. And the Red signal at the bottom shows the whole time period of the PWM signal which 50uS(20KHz) 

    const ftm_user_config_t flexTimer_pwm_InitConfig_new =
    {
        {
            true,  // Software trigger state            -- ENABLED
            false,  // Hardware trigger 1 state         -- DISABLED
            false,  // Hardware trigger 2 state         -- DISABLED
            false,  // Hardware trigger 3 state         -- DISABLED
            true,   // Max loading point state          -- update at counter = MOD
            false,   // Min loading point state          -- update at counter = 0 (CNTIN)
            FTM_SYSTEM_CLOCK, // Update mode for INVCTRL register
            FTM_PWM_SYNC,     // Update mode for SWOCTRL register -- SW sync only
            FTM_PWM_SYNC,     // Update mode for OUTMASK register -- SW sync only
            FTM_SYSTEM_CLOCK, // Update mode for CNTIN register
            true,   // Automatic clear of the trigger   -- auto clear after sync fires
            FTM_WAIT_LOADING_POINTS, // Synchronization point -- wait for loading point
        },
        FTM_MODE_EDGE_ALIGNED_PWM,
        FTM_CLOCK_DIVID_BY_128,
        FTM_CLOCK_SOURCE_SYSTEMCLK,
        FTM_BDM_MODE_00,
        false,
        true
    };

    FTM_DRV_SetSync(3, &(flexTimer_pwm_InitConfig_new.syncMethod));         // Update the FTM 3 Synchronization Configuration



// the following function updates the registers in an ISR routine
uint8_t private_hal_mc_actuate_set_pwm_mask(uint8_t ui8OutMask, uint16_t ui16SwCtrl)
{

    // Apply Mask
    FTM3->OUTMASK = (uint32_t)ui8OutMask;
    FTM3->SWOCTRL = (uint32_t)ui16SwCtrl;
    FTM3->SYNC |= FTM_SYNC_SWSYNC_MASK;
    return 1;
}

[Qazi]

@PetrS Earlier, I was using the following configuration. With this configuration SYNCHOM is set to 0. I faced a problem that the commutation continues to work for 1 hour to 1 day but during this time period, their used to come a time where the BLDC motor used to be stopped. After debugging, I found out that the OUTMASK gets updated but SWOCTRL used to be on the old value. And that lead to Motor Bridge in a state where no LOW side MOSFET is active and hence the motor stopped. With the new configuration I mentioned above, it is working fine for over a weak now. Could you shed some light on what could have gone wrong.
Our understanding was that maybe the clock was on the boundary when OUTMASK is updated and SWOCTRL is left behind but it still doesnt explain that with next clock boundary, it should also get updated, but it didn't.
It would be awesome if you have an answer for it  

    const ftm_user_config_t  flexTimer_pwm_InitConfig =
    {
        {
            true,   // Software trigger state
            false,  // Hardware trigger 1 state
            false,  // Hardware trigger 2 state
            false,  // Hardware trigger 3 state
            true, // Max loading point state
            false, // Min loading point state
            FTM_SYSTEM_CLOCK, // Update mode for INVCTRL register
            FTM_SYSTEM_CLOCK, // Update mode for SWOCTRL register
            FTM_SYSTEM_CLOCK, // Update mode for OUTMASK register
            FTM_SYSTEM_CLOCK, // Update mode for CNTIN register
            true, // Automatic clear of the trigger
            FTM_WAIT_LOADING_POINTS, //  Synchronization point
        },
        FTM_MODE_EDGE_ALIGNED_PWM, //!< Mode of operation for FTM
        FTM_CLOCK_DIVID_BY_128, // FTM clock prescaler
        FTM_CLOCK_SOURCE_SYSTEMCLK,   // FTM clock source
        FTM_BDM_MODE_00, // FTM debug mode
        false, // Interrupt state
        true // Initialization trigger
    };

[PetrS · Accepted solution]

Hi,

there is little difference between MOD/CTIN/CnV and OUTMASK/INVCTRL/SWOCTRL registers synchronization. 
While the first group allow an update of registers with buffered value on selected loading points the second one not and update happens on SW/HW trigger.

See OUTMASK/SWOCTRL register synchronization flowcharts in respective chapters of the device RM for more info.
47.5.13.7 OUTMASK register synchronization
47.5.13.9 SWOCTRL register synchronization

BR, Petr

[Qazi]

Ok that makes sense. You saved me from a lot of headache. Thank you so much