STCU2 internal errors and SPD-BIST BIST_DIAGNOSTIC_CFG

[FabioG]

Hi There,

I have some questions:

1) I didn't find too much  in Safety Mechenisms regarding Bist, and regarding "garage" use case SPD-BIST BIST_DIAGNOSTIC_CFG of Online Bist. I don't find anything. Could you please tell me if this functionality is mandatory (I'm afraid I don't have enough information about SMs ) ?

2) Regarding STCU2_ERR internal errors: INVPSW, ENGESW, WDTOSW, LOCKESW

which is the status of STCU2 after them? do I have to perform a destructive reset or Retry  Bist Run, or nothing?

3) Same question if  Bist_GetExecStatus(BIST_SAFETYBOOT_CFG)=BIST_INTEGRITY_FAIL...which is the status of STCU2 after it?  do I have to perform a destructive reset or Retry  Bist Run, or nothing?

Best Regards,

Fabio

[RadoslavB]

Hi Fabio,

ad 1)
BIST execution is proposed to check whether there are any latent faults in on-chip peripherals (LBIST) and memories (MBIST). It is mandatory to provide evidence of your system robustness against latent faults as required by functional safety standards.

For more information, please collect information from BIST User Manual, S32K3_Bist_Configurations.xlsx  included in the /doc folder and S32K3XX_SAF_BIST_ProfileReport.xlsx included in the quality pack.

BIST Diagnostic configuration has full coverage for latent faults checked by all available LBIST and MBIST, therefore this configuration has longest execution time. 

Our proposal is to execute this configuration in the application phase where there are not too many active tasks or no time critical events are expected to be proceeded – that’s what we call “garage” use case, we expect that the car is parked and only a few non-critical tasks are active.


ad 2)
For each error status you can configure mapping to Recoverable or Unrecoverable fault mapping.
Recoverable fault mapping path is to FCCU, please read eMcem UM – NCF_5 faults description.
Unrecoverable fault mapping path is to MC_RGM, therefore reset reaction is performed.

For the Recoverable fault mapping you need to configure NCF_5 to one of the R1, R2  or R3 reaction – please read SAF Safety Manual for more details.
In case of the internal STCU2 error we recommend to perform the reset and try to execute the BIST again.
If the error will occur all the time, we need to reproduce on our side – more details are needed, which BIST configuration is executed, chip derivative, SAF release version and if it is executed from the SAF Demo example or your application.


ad 3)
Integrity fail is internal error coming from the BIST API function, there is no connection to ERR_STAT register.
This error represents the problem that some of LBIST/MBISTs which were supposed to be executed has been not finished.

We recommend retrying the execution.
If the error will occur all the time, we need to reproduce on our side – more details are needed, which BIST configuration is executed, chip derivative, SAF release version and if it is executed from the SAF Demo example or your application.


Please try to check all proposals required before the BIST execution as described in the BIST User Manual.


Best Regards,
Radoslav

[FabioG · Accepted solution]

• At Point 2 you say (Note we don't use SAF, we only check SPD BIST functionalities):

"For the Recoverable fault mapping you need to configure NCF_5 to one of the R1, R2  or R3 reaction – please read SAF Safety Manual for more details."

Question: Is it  "EMCEM_DCM_NCF_5_STCU_NCF(ID 73) the one and only recoverable (if configured so) Fault Line to manage for recoverable faults?

if This is true, (a) Is this Line   triggered when Bist_GetExecStatus(...) = BIST_FAILED (Bist_GetFailRDs returns all valid domain masks)?

(b)Is This line triggered when Bist_GetExecStatus(...) = BIST_INTEGRITY_FAIL (when partial Bist_GetFailRDs () masks are returned)?

(c) I think this line is not triggered when Bist_GetExecStatus(...)=BIST_ERROR, because STCU2 has an internal error, isnt'it ?

• At point 2) you say : "In case of the internal STCU2 error we recommend to perform the reset and try to execute the BIST again."

Question: How can I count the number of resets if Bist_Run() returns ST_DONE as reset reason, and the ECC ram needs to be reinitialized due to the MBIST? I have no register or ram partitions where I can place a counter that retains it's value after a ST_DONE bist reset...

• At point 3) you say "Please try to check all proposals required before the BIST execution as described in the BIST User Manual."

Question: do you mean raccomandations at  "53.1.14
Modules operation during/post Self-Test"," 53.1.15
Reset events and configurations while Self-Test", "53.1.16
Software considerations before Self-Test " at pp 1892.1893 or S32K3xx reference manual ?

Best Regards,

Fabio

[RadoslavB]

According to the description of the faults from RM I would say yes, only EMCEM_DCM_NCF_5_STCU_NCF is set for all non-critical faults (recoverable) from STCU2.

If Bist_GetExecStatus() returns BIST_FAILED it means that at least one Recoverable or Unrecoverable fault has been reported via ERR_STAT - UFSF, RFSF bits.
So when UFSF is set => MC_RGM reset is forced
If RFSF is set => EMCEM_DCM_NCF_5_STCU_NCF is set

BIST_INTEGRITY_FAIL - after BIST execution for particular BIST configuration it is checked whether all LBIST and MBIST within the configuration has been executed properly (no matter if BIST result was success or fail), if not the integrity fail is reported.

BIST_ERROR - there is path into FCCU for any fault from ERR_STAT which has been configured as Recoverable.


Storing data during full MBIST - there is no way how store the data in SRAM as with BIST Diagnostic configuration whole SRAM content is corrupted.
However, you can store into the data into Flash or use external memory.


Recommendations before BIST execution - I think Bist UM is sufficient to follow, chapter Self-Test prerequisites.



Kind Regards,
Radoslav