Hello,
1. How can BIST errors be injected to simulate the detection of errors during the BIST self-test process?
You can only inject the fault to STCU ERR register to test the reaction path from STCU to FCCU and so on. No physical fault injection to BIST is possible from SW.
Based on my reading of the reference manual, the BISTs are executed sequentially one after another.
After each BIST self-test, a result is generated. If the self-test result fails, two types of errors occur: recoverable and unrecoverable.
Recoverable faults are sent to the FCCU for handling, while unrecoverable faults trigger a destructive reset to the reset module. Therefore:
2. Since the FCCU is also part of the self-test sequence, how does it handle recoverable faults during the self-test process?
It will after the test is complete. While BIST is running no reaction can be taken.
3. Does the FCCU handle recoverable faults during the self-test execution?
No
4. Does the interrupt handler of the FCCU, which handles recoverable faults, interrupt the execution of the self-test?
No
5. When an unrecoverable fault occurs, does it terminate the execution of the remaining BIST sequence and trigger a destructive reset immediately?
No. Reset is triggered by STCU after self test.
During selftest execution the SW is not running, registers and memories are filled with patterns, so there is no point to react anyhow. The STCU will trigger reset after test, and registers will be loaded by default values from UTEST and TEST memory. Then FCCU fault will be latch on STCU ERR register content. And only after that you / FCCU can perform any action.
Best regards,
Peter
