S32k344 legacy fifo with DMA and without interrupt

[sbidkar]

int main(void)

{

uint32_t * pu32CANFIFO1_RegAddress = (uint32_t *)(IP_CAN_0_BASE + 0x80);

uint32_t * pu32FIFO_Data = &FlaxCAN_u16DMA_FifoBuffers[0];

//FLEXCAN_Type * const psFlexCANBase = IP_CAN_0;

/* Write your code here */

// 1. Init Clock, Resource Manager, Pin mux (Siul2_Port_Ip_Init), etc.

Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);

Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);

Dma_Ip_Init(&Dma_Ip_Sa_xDmaInitPB);

Rm_Init(&Rm_Config);

// 2. Install and enable DMA interrupt and FlexCAN interrupt

// IntCtrl_Ip_InstallHandler(DMATCD0_IRQn, Dma0_Ch0_IRQHandler, NULL_PTR);

// IntCtrl_Ip_EnableIrq(DMATCD0_IRQn);

// IntCtrl_Ip_InstallHandler(FlexCAN0_1_IRQn, CAN0_ORED_0_31_MB_IRQHandler,NULL_PTR);

// IntCtrl_Ip_EnableIrq(FlexCAN0_1_IRQn);

// 3. Init DMA

//Dma_Ip_Init(&Dma_Ip_xDmaInitPB);

Dma_Ip_LogicChannelTransferListType asDmaCh1TransferList[2] =

{

{DMA_IP_CH_SET_SOURCE_ADDRESS, (uint32_t)pu32CANFIFO1_RegAddress},

{DMA_IP_CH_SET_DESTINATION_ADDRESS, (uint32_t)pu32FIFO_Data}// (uint32_t)P1OS_Cpu_ConvertLocalAddress(&pu32FIFO_Data[0])}

};

Dma_Ip_SetLogicChannelTransferList(SA_DMA_LOGIC_CH_0, asDmaCh1TransferList, 2);

Dma_Ip_SetLogicChannelCommand(SA_DMA_LOGIC_CH_0 , DMA_IP_CH_SET_HARDWARE_REQUEST);

// 4. Init FlexCAN0

FlexCAN_Ip_Init(INST_FLEXCAN_0, &FlexCAN_State0, &FlexCAN_Config0);

// 5. Configure Rx FIFO (legacy)

FlexCAN_Ip_SetRxMaskType_Privileged(INST_FLEXCAN_0,FLEXCAN_RX_MASK_INDIVIDUAL);

FlexCAN_Ip_ConfigRxFifo_Privileged(INST_FLEXCAN_0,FLEXCAN_RX_FIFO_ID_FORMAT_A , &CAN0_FIFO_IdFilterTable[0]);

// Configure individual mask for first filter (accept range 0x50–0x5F)

FlexCAN_Ip_SetRxIndividualMask(INST_FLEXCAN_0, 0, 0x7F0<<19); // mask for first ID in Filter table 0x50 to 0x5F

// Optional: MB-based receive setup

// FlexCAN_Ip_ConfigRxMb(INST_FLEXCAN_0, RX_MB_IDX, &rx_info, 0x20u); // uncomment for MB

// 6. Start FlexCAN controller

FlexCAN_Ip_SetStartMode(INST_FLEXCAN_0);

// 7. Send an initial dummy TX message via MB

FlexCAN_Ip_Send(INST_FLEXCAN_0, TX_MB_IDX, &tx_info, TX_MSG_ID, dummyData);

// Read Rx FIFO (initial read)---->DMA has transferred data from RxFIFO to rxFifoData

FlexCAN_Ip_RxFifo(INST_FLEXCAN_0, &rxFifoData);

// Read Rx MB (initial read)

// FlexCAN_Ip_Receive(INST_FLEXCAN_0, RX_MB_IDX, &rxData, FALSE); // uncomment for MB receive

while (1) {

}

}

the code is working with interrupt but not without interrupt
source and destination address are configured
please suggest better solution

[PetrS]

Hi,

RTD driver is written in that way.  FlexCAN_Ip_RxFifo configs DMA channel to perform single read from RXFIFO and clear request. DMA interrupt should be enabled, which calls DMA_Can_Callback0 (for CAN0 instance)->FlexCAN_CompleteRxMessageFifoData, that check for DMA error, do some bit manipulation on data buffer and finally calls FlexCAN callback to notify user about the result. In this callback you can call FlexCAN_Ip_RxFifo to reenable DMA channel again.
If you wont to have different behavior, you can modify driver, which is not recommended, or do own implementation.

BR, Petr