S32K394 BIST/STCU reset behavior after normal self-test completion

[SBalaji]

Hello Team.

We are using S32K394 with S32K3 SAF 1.0.5 and reviewing S32K3_SAF_BIST_UM Rev. 11.0.

From the SAF BIST documentation, we understand that:

1. Normal online/runtime BIST execution ends with functional reset.
2. Destructive reset is mentioned only for configured unrecoverable LBIST/MBIST fault cases
3. We do find an explicit documentation that normal STCU self-test completion can be configured to use RESET_b and cause POR / destructive reset. [Reference: S32K396RM.pdf, Rev 4 11/2024 -  Section : 29.2.3.2 Chip action after reset event - NOTE]
4. Could you please advise/clarify which registers / fields / module configuration are used to configure RESET_b assertion?
   We would appreciate a register-level or reference-manual-level pointer for S32K394.

[danielmartynek · Accepted solution]

Hello @SBalaji,

1: Yes.

2: Yes.

3: Even when the reset_b assertion is enabled, it remains a functional reset, not a destructive reset or power‑on reset (POR).
All functional resets assert reset_b. The only exception is STCU2 ST_DONE, where this behavior is configurable.

danielmartynek_0-1777968407058.png

4: Refer to the Reference manual, 

• Section 49.1.13 Self-Test programming sequence. Step 5. Configure ERCTRL[ERASSERT] register bit in MC_RGM to achieve desired behaviour of Reset Pin as documented in Reset Section and Pad States Section.
• Table 22. SELFTEST(MC_RGM.ERCTRL[ERASSERT] configured as 1).
• 29.10.1 Reset pin control during self-test

Regards,

Daniel