S32K358 memory map

[liyongfeng]

Why are the addresses of the ITCM blocks the same in S32K3XX_memory_map.xlsx? The same applies to the DTCM blocks.

Start address [Hex]	End address [Hex]	Max size [KB]	Description	Cache mode at Reset	S32K358
0x00000000	0x0000FFFF	64	ITCM_0	non-cacheable	64
0x00000000	0x0000FFFF	64	ITCM_1	non-cacheable
0x00000000	0x0000FFFF	64	ITCM_2	non-cacheable	64
0x00000000	0x0000FFFF	64	ITCM_3	non-cacheable

0x20000000	0x2001FFFF	128	DTCM_0	non-cacheable	128
0x20000000	0x2001FFFF	128	DTCM_1	non-cacheable
0x20000000	0x2001FFFF	128	DTCM_2	non-cacheable	128
0x20000000	0x2001FFFF	128	DTCM_3	non-cacheable

[danielmartynek]

HI @liyongfeng,

On S32K358:

• ITCM_0 and DTCM_0 are accessible via frontdoor from CM7_0 and CM7_1 operating in lockstep mode.
• ITCM_2 and DTCM_2 are accessible via frontdoor from CM7_2.

For details, refer to the Reference Manual, Figure 9: Block Diagram – S32K338, S32K358, S32K356, S32K348, and S32K328.

[Henrik-Wires · Accepted solution]

There is one ITCM/DTCM memory regions (Instruction/Data Tightly-Coupled Memory) per core, local to the core.

The memory map is common for the whole range of CPUs so you see 4 in the memory map as that is the max number of cores in the CPU range covered by the document.

The same memory regions is also available at "backdoor" addresses for accessing the memory of a specific core.