S32K358 LockStep Core1

[darknite2023]

Hi.

I am using a S32K3X8EVB-Q289 devkit board and have a question regarding lockstep (which is enabled):

• Lockstep core0's PRTN0_CORE0_STAT register shows that its clock is active.
• Lockstep core1's PRTN0_CORE1_STAT register shows that its clock is inactive.

Just wondering if the lockstep's 2nd core needs to be explicitly configured to run i.e. enable its clock? Or, the fact that lockstep is enabled,  the contents of locktstep core1's PRTN0_CORE1_STAT register is not valid?

Thanks in advance.

[bryan_brauchler · Accepted solution]

Hello,

When configured for lockstep, the cores will be configured to run in lockstep before being released from reset. Hence the Core1 registers have no effect.

Best,

Bryan

[darknite2023]

Hi Bryan. Thanks for the response and clarifying my doubt. As a suggestion, it would be nice to state this in the PRTN section of the S32K3XX RM.