S32K358 - GMAC Clock Configuration

[sathishkumar_sunmugavel]

Hi Everyone,

I have a few questions regarding the GMAC clocking configuration.

In my setup, PTB3 is configured as an output pin for RGMII_TXCLK, and PTC16 is configured as an input pin for RGMII_RXCLK. This configuration is confirmed from the attached Excel sheet.

According to the pin descriptions:

• PTB3 can function as either an input or output for GMAC0_MII_RMII_RGMII_TX_CLK

             sathishkumar_sunmugavel_0-1760251864899.png

• PTC16 can function as an input for GMAC0_MII_RGMII_RX_CLK.

             sathishkumar_sunmugavel_1-1760251936647.png

I am using the RGMII interface, which requires a 125 MHz clock input for both EMAC_CLK_RX and EMAC_CLK_TX. From my understanding, only EMAC_MII_RMII_TX_CLK can be used as the clock input.

If this understanding is incorrect, please clarify how these two clocks should be provided.

• EMAC_MII_RMII_TX_CLK → MC_CGM_MUX7 → EMAC_CLK_RX

• EMAC_MII_RMII_TX_CLK → MC_CGM_MUX8 → EMAC_CLK_TX

sathishkumar_sunmugavel_2-1760252344261.png

Up to this point, everything is clear. However, the table below is a bit confusing as it lists the source, destination clock, and port details.

1. The IBE bit is set for all the listed ports — could you please explain what this indicates?

2. PTC16 appears to be used between GMAC_MII_RGMII_RX_CLK and GMAC_TS_CLK but I used PTC16 as RGMII Rx clock pin — could you clarify this connection?

3. Based on my understanding, PTB3 and PTC16 can be used as the RGMII Tx/Rx clock pins connected to the PHY. Additionally, the clock source EMAC_MII_RMII_TX_CLK is internally connected to EMAC_CLK_RX and EMAC_CLK_TX through MUX7 and MUX8, respectively. However, the information in the table seems inconsistent with this understanding — could you please clarify?
   
   

   sathishkumar_sunmugavel_3-1760253362178.png

Best Regards,
Sathish.

[PavelL · Accepted solution]

Hello @sathishkumar_sunmugavel ,

Please find answers to your questions below. FYI, you use S32K3 RM Rev 6, the latest one is Rev. 11.

I run successfully RGMII 100Mbps on S32K358EVB-Q289, with external TJA1103 on SABRE connector.

1. Here's screenshot of Pins:

PavelL_0-1760353715569.png

2. Clocks can be tricky a little bit. RGMII TX_CLK shall be an output, RGMII RX_CLK shall be an input. There's an internal divider 2, so TX_CLK need to be doubled. 

PavelL_1-1760353859390.png

For GMAC 1Gbps change the clocks accordingly: 25MHz -> 125MHz ; 50MHz -> 250MHz

3. And the last point, it's necessary to set up clock muxes also in your code, before gmac init. I do it usually as the very first rows in the code:

PavelL_2-1760354079287.png

I do not use Table 116 (in RM Rev 6).

Best regards,

Pavel

[sathishkumar_sunmugavel]

Hi @PavelL 

Thank you so much for the valuable inputs. The issue is resolved after adding the below line. 

IP_DCM_GPR->DCMRWF1|=DCM_GPR_DCMRWF1_MAC_CONF_SEL(0x01) |DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_MASK;

But could you please confirm why this tx clock loop back is required?

Best Regards,
Sathish.

[PavelL]

Hello @sathishkumar_sunmugavel ,

This is related to the GMAC IP from Synopsys.

This bit allows the MAC to internally loop back its own TX clock as the input clock - which is necessary to initialize MAC in RGMII mode.

Best regards,

Pavel

[sathishkumar_sunmugavel]

Hi @PavelL 

Got it. Thanks!!!

[sathishkumar_sunmugavel]

There is no PHY in my setup. It's MAC-MAC connection. 

sathishkumar_sunmugavel_0-1760258913178.png

1. In that case, Do I need to consider this PHY_INTF_SEL signal input to GMAC module?
2. Can I use PLL_AUX_CLK with 125MHz for both CLK_TX_I and CLK_RX_I?
3. CLK_TX_I and CLK_RX_I are connected by internal muxing, and PTB3 should be configured as output from GMAC for RGMII TX_CLK and PTC16 should be configured as input to GMAC RGMII RX_CLK. Is this understanding, correct?