Hi Julián,
Thank you for your response. I wanted to share my findings in case anyone else encounters a similar issue.
After further debugging, I was able to resolve the problem by making two key modifications:
- Before calling Siul2_Port_Ip_Init, I applied the following configuration:
IP_DCM_GPR->DCMRWF1 = (IP_DCM_GPR->DCMRWF1 & ~DCM_GPR_DCMRWF1_EMAC_CONF_SEL_MASK) | DCM_GPR_DCMRWF1_EMAC_CONF_SEL(2U);
- In the clock configuration, I set the dividers for EMAC_TX_CLK and EMAC_RX_CLK to 2, reducing their frequencies to 25 MHz.
After applying these changes, data transmission started working correctly.
For reference, the corrupted data issue observed when TX_CLK was not connected remains an interesting behavior, but after properly setting up the reference clocks and configuration registers, the system now operates as expected.
I hope this helps others who might face similar issues.
Best regards,
Mehmet Fatih