S32K344 - ECC Correctable and Uncorrectable errors Memory 10 (SBC10-NCE10)

[fede_ls]

Hello,

I'm in the process of writing a driver to read diagnostic data from the Error Reporting Module.

I noticed that the ERM Status Register 1 corresponding to Memory 10 is continuously detecting Single Bit Correction Events and Non-Correctable Error Events.

As a result, the error counter CORR_ERR_CNT10 reaches 0xFF immediately and both EAR10 and SYN10 appear to be confirming some kind of error (please refer to the image below).

This is the only Memory Area affected by this behaviour. Attempting to clear the SBC10 and NCE10 fields results in an almost immediate NCE10 bit flip, followed after no more than 10ms by SBC10 bit flipping, indicating a consistent correction and notification on error event.

My current approach to initialize this module consist in attempting to clear all Status Reporting fields and not using interrupt based notification on ECC errors. Not attempting to clear the Status Reporting Register on system power-on results in the same behaviour.

I have a few questions

1. Why is it happening?
2. Is Memory 10 related to "Cortex-M7_0 ITCM" according to Table 293?
3. If Memory 10 is indeed related to Core#0 ITCM and considering that I'm using a lockstep microcontroller and that this issue doesn't appear to affect the checker core that Cortex-M7_1 ITCM, does it mean that Core0 ITCM is faulty?

[danielmartynek]

Hi @fede_ls,

Just to be sure, is PRTN1_COFB0_STAT[BLOCK23] running?

[fede_ls]

I just checked. PRTN1_COFB0_STAT is set to 0x7EFF001F, indicating that PRTN1_COFB0_STAT[BLOCK23] is running.
Do you have any insight on what might be causing this issue?

[danielmartynek]

Hi @fede_ls,

Thank you for the confirmation.

Could you please verify whether the ITCM is properly initialized in the startup code (startup_cm7.s, in the ITCM_Init section)?

I noticed an error being detected at address 0x508.
Can you check what code is located at that address in the .map file?

Please note that ITCM can be reinitialized at any time via a 64-bit write to the memory.
Therefore, even if a read error occurred, it could potentially be resolved by reinitializing the ITCM.

If a genuine ECC error can be ruled out, the issue might be related to the system clock configuration.
NXP does not guarantee proper MCU functionality if the system clock settings do not adhere to the division ratios specified in the clock options.
For example, refer to Table 157, Option A – High Performance Mode (CORE_CLK @ 160 MHz).

We strongly recommend using only the predefined clock options exactly as specified to ensure reliable operation.

Regards,

Daniel

[fede_ls]

Hi Daniel,

Could you please verify whether the ITCM is properly initialized in the startup code (startup_cm7.s, in the ITCM_Init section)?

I'm using the default S32DS CMSIS Core Device Startup File startup_ARMCM7.c, I'm attaching the standard .c file to this reply.

I checked the "Example_Siul2_Port_Ip_Example_S32K344_ITCM_DTCM_S32DS3.4 RTD300.zip" to get an idea of what it looks like (as shown in screenshot below for for future reference).

Does it mean that ITCM and DTCM are not initialized by default with non-RTD startup files?

I made sure that SCB->ITCMCR shows that ITCM is indeed enabled and I tried to disable->reenable on startup. 

I noticed an error being detected at address 0x508.
Can you check what code is located at that address in the .map file?

If a genuine ECC error can be ruled out, the issue might be related to the system clock configuration.
NXP does not guarantee proper MCU functionality if the system clock settings do not adhere to the division ratios specified in the clock options.
For example, refer to Table 157, Option A – High Performance Mode (CORE_CLK @ 160 MHz).

I currently successfully configured the clocks to Option A and verified that their configuration is indeed applied. 

[danielmartynek · Accepted solution]

Hi @fede_ls,

ECC initialization is device-specific and therefore not included in default startup codes. It is the responsibility of the developer to implement ECC setup according to the requirements of the target hardware. Importantly, ECC must be properly initialized before any read operations are performed on the memory.

[fede_ls]

Hi daniel, thank you for your support.
Following your advice, I solved my issue with implementing "Example 6. ITCM initialization by core" contained in AN13388 "S32K3 Memories Guide".