S32K144 RAM test failed in startup phase

[LijieDu]

when I am doing the ram test below in startup phase, it always resets in step3, I can't find the reason,

pls help me/(ㄒoㄒ)/~~

-----------------------↓----------------↓-----------------------------------

;;RAM TEST (__RAM_START=0x1FFF9000 /__RAM_END=0x20006FFF)
;;STEP 1 - Write background 00 with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END

SUBS R2, R2, R1
SUBS R2, #1
BLE .TS1_2

MOVS R0, #0
MOVS R3, #4
.TS1_1: ;TEST STEP 1.1
STR R0, [R1]
ADD R1, R1, R3
SUBS R2, #4
BGE .TS1_1
.TS1_2: ;TEST STEP 1.1

;;STEP 2 - Verify background and write inverted background 0xFF with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END

SUBS R2, R2, R1
SUBS R2, #1
BLE .TS2_2

LDR R3, =0xFFFFFFFF
.TS2_1: ;TEST STEP 2.1
LDR R0, [R1]
CMP R0, #0
BNE Fst_RAMTSTFAIL

STR R3, [R1]
ADDS R1, R1, #4
SUBS R2, #4
BGE .TS2_1
.TS2_2: ;TEST STEP 2.2

;;STEP 3 - Verify inverted background 0xFF and write background 0x00 with addresses increasing
LDR R1, =__RAM_START
LDR R2, =__RAM_END

SUBS R2, R2, R1
SUBS R2, #1
BLE .TS3_2

MOVS R4, #0
.TS3_1: ;TEST STEP 3.1
LDR R0, [R1]
LDR R3, =0xFFFFFFFF
CMP R0, R3
BNE Fst_RAMTSTFAIL

STR R4, [R1]
ADDS R1, R1, #4
SUBS R2, #4
BGE .TS3_1
.TS3_2: ;TEST STEP 3.2

;;STEP 4 - Verify background 0x00 and write inverted background 0xFF with addresses

....

;;STEP 5 - Verify inverted background and write background with addresses decreasing

....

[danielmartynek]

Hi @LijieDu,

Do you know the address where the MCU resets?

If the MCU is resetting unexpectedly, it’s likely due to a core lockup, which sets the RCM_SRS[LOCKUP] flag. This typically happens when a fault (such as a HardFault) occurs and there is no valid HardFault_Handler implemented in your project.

To improve debugging and catch these exceptions more effectively, I recommend implementing a custom HardFault_Handler. 

Regards,

Daniel

[LijieDu]

Hi @danielmartynek 

Thanks for your answer, I have implemented a HardFault handler and it didn't run to it.

The code is used on s32k118 and I reuse it on s32k144,  the difference is RAM_START and RAM_END definition.

Is there something wrong with the code or I just ignore something else with s32k144?

[danielmartynek]

Hi @LijieDu,

Can you still identify the reset source?

[LijieDu]

I find the reset cause, but still confused about it, I even didn't config the wdog.

[danielmartynek · Accepted solution]

Hi @LijieDu,

The WDOG is enabled by default out of reset:

It is disabled in the Startup:

Regards,

Daniel

[LijieDu]

Hi @danielmartynek  

I do the ram test before disable the wdog, so it resets!

It didn't happen on s32k118(ram size is 23k), because the ram to be tested is less than 32k144(ram size is 64k).

I disable the wdog before ram test, and it run normally

thanks bro

[LijieDu]

Hi @danielmartynek  

It is so hard to find the reset cause! That is why I am seeking help here

When executing the reset handler (reset vector table), the MCU is blank, and then it initializes registers R1-R12 and starts the RAM test. Nothing else is done.