S32K322_Pwm _Issue

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S32K322_Pwm _Issue

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gadilinga
Contributor III

Hi ,

Currently I'm Working On S32K322 Micro EMIOS Pwm But It's Not getting Any Signle From Pwm and  I Configured Port Pin Level Also Its Getting Continues Low,  When I select the Emios_0_CH[0]_X_OUT.  another Thing I Was  worked On S32K344 Board Its Working. But In S32K322 Board Its  not Working so That Port Pin Mode Made As GPIO That Time Its Toggling. SO In Another Case we Are using Core_Clk for Emios Pwm As Mention In S32Kxx Reference  Manual Same Thing i Did In S32K344 Its Working But In s32K322 I was Not Working So Again I used Another Clock FXOSC_Clk For Pwm Mcu Clock Reference also not working So what was issue for this. thank u

gadilinga_0-1725628074258.png

gadilinga_1-1725628503592.png

gadilinga_2-1725628565563.png

 

 

 

 

 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @gadilinga 

This parameter Enables/Disables outputs to continue operation in Debug.

 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @gadilinga 

As shown in the S32K3xx Reference Manual, the only clock source of eMIOS is CORE_CLK and the clock limitations of S32K322 are the same as S32K344. So there should not be a problem with the clock configuration.

Did you configure PLL as the clock source? If so, could you check if the crystal connected to EXTAL and XTAL pins is generating the expected clock signal (I am assuming the board with the S32K322 is a custom board)?

Could you share images of the configurations made for the PWM and MCL driver configurations to check if there is no problem regarding these?

 

BR, VaneB

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gadilinga
Contributor III

Hi @VaneB ,

thank u For Ur Quick response, Yeah As u Assumed correct only we are using S32K322 Customized Board. we Check With External Clk(FXOSC_CLK_40Mhz). And PLL also We Configured. When PLL is not Working it will take Internal FIRC CLk . so Its not getting Pin High. Whatever I shared Here I Configured Its Working In S32K344 But Its Not working In S32k322 board I didn't get Root cause of this Issue. 

gadilinga_0-1725952347556.pnggadilinga_1-1725952387521.pnggadilinga_2-1725952419775.pnggadilinga_3-1725952449722.pnggadilinga_4-1725952486201.png

gadilinga_5-1725952521050.png

 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @gadilinga 

According to the shared images the configurations seem correct, please try from the beginning setting the internal clock (FIRC) as clock source, this is to check if the problem can be caused by the external clock.

I want to check if it is not a hardware problem since the configurations and code work with the S32K344.

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2,766 Views
gadilinga
Contributor III
Hi @VaneB,
Currently We Used Customize Board Was Verified By Nxp Any DifferenceIs there For Eval Board and Customize Board.
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2,764 Views
gadilinga
Contributor III
Hi @VaneB,

Plz guide Us For This Issue I didn't get What was the Root Cause
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2,755 Views
gadilinga
Contributor III

Hi @VaneB , 

Currently Issue Was Resolved, I got Root Cause was Allow Debug Mode when it Make True It was Not Working When I Make it False It was Working. So can I U Give me More Clarity On this. Thank u

gadilinga_0-1726045462543.png

 

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2,735 Views
VaneB
NXP TechSupport
NXP TechSupport

Hi @gadilinga 

This parameter Enables/Disables outputs to continue operation in Debug.

 

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gadilinga
Contributor III
Hi @VaneB,
Yeah! In S32K344 its Enable/Disable But It Working. In S32K322 if Its Enable Pwm output was Not Coming If Its Disable Its working. Another Thing Was Pin getting Low When Enable Debug Mode. So what is Relation B\W if We Allow the Debug Mode In s32K322. Could U Plz Guide US.
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VaneB
NXP TechSupport
NXP TechSupport

Hi @gadilinga 

Could you help me verify that when enabling or disabling the Allow Debug Mode parameter, the code changes are observed?

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gadilinga
Contributor III

Hi @VaneB ,

If I enable the Allow the debug Mode it will Get set Overflow Bit.

gadilinga_0-1726202026384.png

This Is what I Seen in RM.

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