S32K322 FLEXCAN THROUGH DMA

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S32K322 FLEXCAN THROUGH DMA

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vignesh3
Contributor II

ERFCR[ERFEN] this register is not precent in S32K322 controller.

an one more thing and can anyone give me step by step example code for can through dma.

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3,648 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@vignesh3

This part is described in detail in the data sheet.

S32K3xx Reference Manual, Rev. 9, 07/2024:

Senlent_0-1742346595631.png

 

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vignesh3
Contributor II

If message buffer is received a CAN message will it request DMA channel or Is it only legacy fifo is requesting the DMA ?

 

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3,609 Views
vignesh3
Contributor II

How can I know that if peripherals are requesting to the DMA channel or not ?

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3,639 Views
vignesh3
Contributor II

I have one more doubt also, can you tell me when to use Message buffers , Mail boxes and RXFIO(legacy fifo and enhanced fifo)?

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3,635 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@vignesh3

The message buffers and mail boxes you mentioned should be the same concept.
1. When sending, you must use MB.
2. Receiving can be MB or FIFO.
3. Legacy FIFO and Enhanced FIFO cannot be enabled at the same time. The difference is that Enhanced FIFO can be used for CAN FD, while Legacy FIFO cannot support CAN FD.

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vigneshv1
Contributor I

vigneshv1_0-1762166837382.png

Hi @Senlent ,

According to above picture it looks like RxFIFO and mailbox are same is it correct?

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3,489 Views
vignesh3
Contributor II
Hi @Senlent ,

So can I use message buffers for receiving and transmitting through DMA instead of using legacy RX FIFO.

an Is the message buffer address is present in the SRAM area because I have studied that we can use non configured message buffers as SRAM in the application notes ?
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3,473 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@vignesh3

Create a new topic for your new question, this original topic is closed.

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3,665 Views
vignesh3
Contributor II

we are receiving all the CAN messages in this Flexcan_Ip_StateType FlexCAN_BOARD_InitPeripherals_State0; global variable.

the message buffers are implemented in this structure. can anyone tell me how RAM space is assigned as CAN message buffers.

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3,649 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@vignesh3

This part is described in detail in the data sheet.

S32K3xx Reference Manual, Rev. 9, 07/2024:

Senlent_0-1742346595631.png

 

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3,679 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@vignesh3

As you can see that the FlexCAN 0 of S32K322 do supports Enhanced Fido

S32K3xx Referernce Manual, Rev9.9/07/2024, the Table 488.

Senlent_0-1742283835733.png

 

For FlexCAN with DMA used , you may refer to this post by Petr,

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-FlexCAN-Ip-TX-RX-EnhanceRXFIFO-DMA-...

 

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