Hi everyone,
I need to read 4 ADC channels. Two of them are ADC-0 and the other two are ADC-1 channels.
I configured BCTU, PIT, and TRGMUX to ensure continuous conversion.
I want the conversion results to be stored in the buffer I specified with DMA.
Created a list to start the conversion of ADC channels with a single BCTU trigger.
I want to ask here:
Do I need to create four DMA channels for four ADC channels?
Can't I get the result of four ADC channels with a single DMA channel?
解決済! 解決策の投稿を見る。
Hi,
I posted working example at https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-...
Hope it helps.
BR, Petr
Hi,
there is no need to have 4 DMA channels for 4 ADC results. You can configure a list to perform 2 parallel conversions. Refer to chapter 65.3.4 Multiple parallel conversions (MPC) of the RM.
If the DATA_DEST of the trigger selects one of the FIFO, you can read 4 converted results from that selected FIFO using single DMA channel (watermark set to 3).
I put some PIT BCTU ADC DMA example at https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-PIT-BTCU-ADC-DMA-DS3-4-RTD100/ta-p/... but BCTU data register is set as result destination so it would need some modification to follow your need.
BR, Petr
Hi @PetrS,
Thank you for your answer, but my problem persists. I cannot get the ADC conversion result in the buffer I gave to the BCTU unit.
Let me briefly explain what I did.
I configured ADC-0 and ADC-1:
And also i configured related channels
ADC-0:
ADC-1:
BCTU configurations:
TRGMUX and PIT configurations:
DMA configurations:
Even though I made all these configurations, no data is written to the buffer I gave to DMA.
When I check FIFODR1 with debug, I see the data, but FIFO does not run DMA for some reason.
When I reviewed the driver functions, I saw that bctu turns off the DMA hardware request every time the transfer ends in DMA configurations.
To prevent this, the function named Bctu_Ip_FifoDmaHandler is called within the Bctu_Ip_Bctu0Fifo1DmaComplete function. Thus, the DMA hardware request is refreshed.
What I want to ask here is who calls the Bctu_Ip_Bctu0Fifo1DmaComplete function and when. Could it be related to my problem?
What am I missing so that DMA can work and an interrupt occurs in the DMA major loop?
Hi,
I posted working example at https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-...
Hope it helps.
BR, Petr
Hello!
I have similar setup (but with s32k311 and three ADC channels on a single instance) and related question. I am trying to have BCTU trigger DMA transfer of FIFO1 conversion results and then DMA to trigger interrupt. None of this happens - BctuDmaFifo1 is empty and no interrupt from dma. With BCTU interrupt notification it works correctly.
P.S. DMA Global/transfer config is disabled because I can see that it's set in Bctu_FifoSetupDma().
Can you tell me please what I might be missing here?